Spartan-3 FPGA Family: DC and Switching Characteristics
R
T
CCH
T
CCL
TCK
(Input)
T
TMSTCK
T
TCKTMS
1/F
TCK
TMS
(Input)
T
TDITCK
T
TCKTDI
TDI
(Input)
T
TCKTDO
TDO
(Output)
DS099_06_040703
Figure 37:
JTAG Waveforms
Table 67:
Timing for the JTAG Test Access Port
All Speed Grades
Symbol
Clock-to-Output Times
Description
Min
Max
Units
T
TCKTDO
Setup Times
The time from the falling transition on the TCK pin to data
appearing at the TDO pin
1.0
11.0
ns
T
TDITCK
T
TMSTCK
Hold Times
The time from the setup of data at the TDI pin to the rising
transition at the TCK pin
The time from the setup of a logic level at the TMS pin to the
rising transition at the TCK pin
7.0
7.0
-
-
ns
ns
T
TCKTDI
T
TCKTMS
Clock Timing
The time from the rising transition at the TCK pin to the point
when data is last held at the TDI pin
The time from the rising transition at the TCK pin to the point
when a logic level is last held at the TMS pin
0
0
-
-
ns
ns
T
TCKH
T
TCKL
F
TCK
TCK pin High pulse width
TCK pin Low pulse width
Frequency of the TCK signal
JTAG Configuration
Boundary-Scan
5
5
0
0
∞
∞
33
25
ns
ns
MHz
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in
96
DS099-3 (v2.4) June 25, 2008
Product Specification
XILINX [ XILINX, INC ]
