Spartan-3 FPGA Family: DC and Switching Characteristics
R
Date
05/25/07
Version No.
2.2
Description
Improved absolute maximum voltage specifications in
providing additional overshoot
allowance. Improved XC3S50 HBM ESD to 2000V in
Based on extensive 90 nm production
data, improved (reduced) the maximum quiescent current limits for the I
CCINTQ
and I
CCOQ
specifications
in
Widened the recommended voltage range for the PCI standard and clarified the hysteresis
footnote in
Noted restriction on combining differential outputs in
Updated footnote 1
in
Updated 3.3V VCCO max from 3.45V to 3.465V in
and elsewhere. Reduced t
ICCK
minimum from
0.50μs to 0.25μs in
Updated links to technical documentation.
Clarified dual marking. Added
Added references to
in
and
Removed absolute minimum and added footnote referring to timing analyzer for minimum delay
values. Added HSLVDCI to
and
Updated t
DICK
in
to match largest possible
value in speed file. Updated formatting and links.
11/30/07
06/25/08
2.3
2.4
98
DS099-3 (v2.4) June 25, 2008
Product Specification
XILINX [ XILINX, INC ]
