R
Spartan-3 FPGA Family: Functional Description
transients. Each I/O has two clamp diodes: One diode
extends P-to-N from the pad to V
CCO
and a second diode
extends N-to-P from the pad to GND. During operation,
these diodes are normally biased in the off state. These
clamp diodes are always connected to the pad, regardless
of the signal standard selected. The presence of diodes lim-
its the ability of Spartan-3 I/Os to tolerate high signal volt-
ages. The V
IN
absolute maximum rating in
specifies the voltage range that I/Os can tolerate.
DCM
180˚ 0˚
FDDR
D1
Q1
CLK1
Slew Rate Control and Drive Strength
DDR MUX
Q
D2
Q2
CLK2
Two options, FAST and SLOW, control the output slew rate.
The FAST option supports output switching at a high rate.
The SLOW option reduces bus transients. These options are
only available when using one of the LVCMOS or LVTTL
standards, which also provide up to seven different levels of
current drive strength: 2, 4, 6, 8, 12, 16, and 24 mA. Choos-
ing the appropriate drive strength level is yet another means
to minimize bus transients.
shows the drive strengths that the LVCMOS and
LVTTL standards support.
DS099-2_02_070303
Figure 6:
Clocking the DDR Register
Pull-Up and Pull-Down Resistors
The optional pull-up and pull-down resistors are intended to
establish High and Low levels, respectively, at unused I/Os.
The pull-up resistor optionally connects each IOB pad to
V
CCO
. A pull-down resistor optionally connects each pad to
GND. These resistors are placed in a design using the
PULLUP and PULLDOWN symbols in a schematic, respec-
tively. They can also be instantiated as components, set as
constraints or passed as attributes in HDL code. These
resistors can also be selected for all unused I/O using the
Bitstream Generator (BitGen) option UnusedPin. A Low
logic level on HSWAP_EN activates the pull-up resistors on
all I/Os during configuration.
The Spartan-3 I/O pull-up and pull-down resistors are signif-
icantly stronger than the "weak" pull-up/pull-down resistors
used in previous Xilinx FPGA families. See
for equivalent resistor strengths.
Table 6:
Programmable Output Drive Current
Signal
Current Drive (mA)
Standard
2
4
6
8
12
16
(IOSTANDARD)
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
-
-
-
-
24
-
-
-
Boundary-Scan Capability
All Spartan-3 IOBs support boundary-scan testing compat-
ible with IEEE 1149.1 standards. During boundary scan
operations such as EXTEST and HIGHZ the I/O pull-down
resistor is active. For more information, see
and refer to the “Using
Boundary Scan and BSDL Files”
chapter in
SelectIO Interface Signal Standards
The IOBs support 18 different single-ended signal stan-
dards, as listed in
Furthermore, the majority of
IOBs can be used in specific pairs supporting any of eight
differential signal standards, as shown in
To define the SelectIO
™
interface signaling standard in a
design, set the IOSTANDARD attribute to the appropriate
setting. Xilinx provides a variety of different methods for
applying the IOSTANDARD for maximum flexibility. For a full
description of different methods of applying attributes to
control IOSTANDARD, refer to the “Using
I/O Resources”
chapter in
Keeper Circuit
Each I/O has an optional keeper circuit that retains the last
logic level on a line after all drivers have been turned off.
This is useful to keep bus lines from floating when all con-
nected drivers are in a high-impedance state. This function
is placed in a design using the KEEPER symbol. Pull-up
and pull-down resistors override the keeper circuit.
ESD Protection
Clamp diodes protect all device pads against damage from
Electro-Static Discharge (ESD) as well as excessive voltage
DS099-2 (v2.4) June 25, 2008
Product Specification
15
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