R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 1: XC4000E and XC4000X Series Field Programmable Gate Arrays
Logic
Cells
152
238
466
608
770
950
1368
1862
2432
2432
3078
3800
4598
5472
7448
Max Logic Max. RAM
Gates
Bits
(No RAM) (No Logic)
1,600
2,048
3,000
3,200
5,000
6,272
6,000
8,192
8,000
10,368
10,000
12,800
13,000
18,432
20,000
25,088
25,000
32,768
28,000
32,768
36,000
41,472
44,000
51,200
52,000
61,952
62,000
73,728
85,000
100,352
Typical
Gate Range
(Logic and RAM)*
1,000 - 3,000
2,000 - 5,000
3,000 - 9,000
4,000 - 12,000
6,000 - 15,000
7,000 - 20,000
10,000 - 30,000
13,000 - 40,000
15,000 - 45,000
18,000 - 50,000
22,000 - 65,000
27,000 - 80,000
33,000 - 100,000
40,000 - 130,000
55,000 - 180,000
CLB
Matrix
8x8
10 x 10
14 x 14
16 x 16
18 x 18
20 x 20
24 x 24
28 x 28
32 x 32
32 x 32
36 x 36
40 x 40
44 x 44
48 x 48
56 x 56
Total
CLBs
64
100
196
256
324
400
576
784
1,024
1,024
1,296
1,600
1,936
2,304
3,136
Number
of
Max.
Flip-Flops User I/O
256
64
360
80
616
112
768
128
936
144
1,120
160
1,536
192
2,016
224
2,560
256
2,560
256
3,168
288
3,840
320
4,576
352
5,376
384
7,168
448
Device
XC4002XL
XC4003E
XC4005E/XL
XC4006E
XC4008E
XC4010E/XL
XC4013E/XL
XC4020E/XL
XC4025E
XC4028EX/XL
XC4036EX/XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Note:
All functionality in low-voltage families is the same as
in the corresponding 5-Volt family, except where numerical
references are made to timing or power.
Description
XC4000 Series devices are implemented with a regular,
flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources, and surrounded by a perimeter
of programmable Input/Output Blocks (IOBs). They have
generous routing resources to accommodate the most
complex interconnect patterns.
The devices are customized by loading configuration data
into internal memory cells. The FPGA can either actively
read its configuration data from an external serial or
byte-parallel PROM (master modes), or the configuration
data can be written into the FPGA from an external device
(slave and peripheral modes).
XC4000 Series FPGAs are supported by powerful and
sophisticated software, covering every aspect of design
from schematic or behavioral entry, floor planning, simula-
tion, automatic block placement and routing of intercon-
nects, to the creation, downloading, and readback of the
configuration bit stream.
Because Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications.
FPGAs are ideal for shortening design and development
cycles, and also offer a cost-effective solution for produc-
tion rates well beyond 5,000 systems per month. For lowest
high-volume unit cost, a design can first be implemented in
the XC4000E or XC4000X, then migrated to one of Xilinx’
compatible HardWire mask-programmed devices.
Taking Advantage of Re-configuration
FPGA devices can be re-configured to change logic func-
tion while resident in the system. This capability gives the
system designer a new degree of freedom not available
with any other type of logic.
Hardware can be changed as easily as software. Design
updates or modifications are easy, and can be made to
products already in the field. An FPGA can even be re-con-
figured dynamically to perform different functions at differ-
ent times.
Re-configurable logic can be used to implement system
self-diagnostics, create systems capable of being re-con-
figured for different environments or operations, or imple-
ment multi-purpose hardware for a given application. As an
added benefit, using re-configurable FPGA devices simpli-
fies hardware design and debugging and shortens product
time-to-market.
6-6
May 14, 1999 (Version 1.6)
XILINX [ XILINX, INC ]
