Spartan and Spartan-XL FPGA Families Data Sheet
R
B
G-LUT
G4
G3
G2
G1
SR
H1
DIN
F4
F3
F2
F1
F4
Logic
F3 Function
of G
F2 F1-F4
F1
G4
Logic
G3 Function
of G
G1-G4
G2
G1
G
D
CK
EC
SR
Q
YQ
H-LUT
Logic
Function
H
H1 of
F-G-H1
F
SR
D
CK
EC
Q
XQ
Y
A
F-LUT
K
EC
Multiplexer Controlled
by Configuration Program
X
DS060_02_0506 01
Figure 2:
Spartan/XL Simplified CLB Logic Diagram (some features not shown)
A CLB can implement any of the following functions:
•
Any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables
Note:
When three separate functions are generated, one of
the function outputs must be captured in a flip-flop internal to
the CLB. Only two unregistered function generator outputs
are available from the CLB.
Flip-Flops
Each CLB contains two flip-flops that can be used to regis-
ter (store) the function generator outputs. The flip-flops and
function generators can also be used independently (see
Figure 2).
The CLB input DIN can be used as a direct input
to either of the two flip-flops. H1 can also drive either
flip-flop via the H-LUT with a slight additional delay.
The two flip-flops have common clock (CK), clock enable
(EC) and set/reset (SR) inputs. Internally both flip-flops are
also controlled by a global initialization signal (GSR) which
is described in detail in
•
•
•
Any single function of five variables
Any function of four variables together with some
functions of six variables
Some functions of up to nine variables.
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
Latches (Spartan-XL Family Only)
The Spartan-XL family CLB storage elements can also be
configured as latches. The two latches have common clock
(K) and clock enable (EC) inputs. Functionality of the stor-
age element is described in
Table 2.
4
DS060 (v1.8) June 26, 2008
Product Specification
XILINX [ XILINX, INC ]
