Spartan and Spartan-XL FPGA Families Data Sheet
R
DIN
GSR
H1
D
C1
C2
SR
C3
EC
C4
EC
Vcc
CK
D
SD
Q
Q
RD
Multiplexer Controlled
by Configuration Program
Multiplexer Controlled
by Configuration Program
DS060_04_081100
DS060_05_041901
Figure 4:
CLB Control Signal Interface
The four internal control signals are:
•
•
•
•
EC: Enable Clock
SR: Asynchronous Set/Reset or H function generator
Input 0
DIN: Direct In or H function generator Input 2
H1: H function generator Input 1.
Figure 5:
IOB Flip-Flop/Latch Functional Block
Diagram
IOB Input Signal Path
The input signal to the IOB can be configured to either go
directly to the routing channels (via I1 and I2 in
Figure 6)
or
to the input register. The input register can be programmed
as either an edge-triggered flip-flop or a level-sensitive
latch. The functionality of this register is shown in
Table 3,
and a simplified block diagram of the register can be seen in
Figure 5.
Table 3:
Input Register Functionality
Mode
Power-Up or
GSR
Flip-Flop
0
Latch
Both
Legend:
X
SR
0*
1*
Don’t care.
Rising edge (clock not inverted).
Set or Reset value. Reset is default.
Input is Low or unconnected (default
value)
Input is High or unconnected (default
value)
1
0
X
CK
X
EC
X
1*
X
1*
1*
0
D
X
D
X
X
D
X
Q
SR
D
Q
Q
D
Q
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals.
Figure 6
shows a simplified functional block diagram of the Spar-
tan/XL FPGA IOB.
6
DS060 (v1.8) June 26, 2008
Product Specification
XILINX [ XILINX, INC ]
