Virtex™ 2.5 V Field Programmable Gate Arrays
R
Revision History
Date
11/98
01/99
02/99
05/99
05/99
07/99
Version
1.0
1.2
1.3
1.4
1.5
1.6
Initial Xilinx release.
Updated package drawings and specs.
Update of package drawings, updated specifications.
Addition of package drawings and specifications.
Replaced FG 676 & FG680 package drawings.
Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, “0” hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added T
IJITCC
parameter, changed T
OJIT
to
T
OPHASE
.
Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for V
CCO
in CS144 package on p.43.
Updated DLL Jitter Parameter table and waveforms, added Delay Measurement
Methodology table for different I/O standards, changed buffered Hex line info and
Input/Output Timing measurement notes.
New TBCKO values; corrected FG680 package connection drawing; new note about status
of CCLK pin after configuration.
Modified “Pins not listed ...” statement. Speed grade update to Final status.
Modified Table 18.
•
•
•
•
•
04/01
2.5
•
•
Added XCV400 values to table under
Minimum Clock-to-Out for Virtex Devices.
Corrected Units column in table under
IOB Input Switching Characteristics.
Added values to table under
CLB SelectRAM Switching Characteristics.
Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in
Table 18.
Corrected
BG256 Pin Function Diagram.
Revised minimums for
Global Clock Set-Up and Hold for LVTTL Standard, with DLL.
Converted file to modularized format. See
section.
Revision
09/99
1.7
01/00
1.8
01/00
1.9
03/00
05/00
05/00
09/00
2.0
2.1
2.2
2.3
10/00
2.4
Virtex Data Sheet
The Virtex Data Sheet contains the following modules:
•
•
DS003-1, Virtex 2.5V FPGAs:
Introduction and Ordering Information (Module 1)
•
•
DS003-3, Virtex 2.5V FPGAs:
DS003-2, Virtex 2.5V FPGAs:
DS003-4, Virtex 2.5V FPGAs:
Module 1 of 4
4
1-800-255-7778
DS003-1 (v2.5 ) April 2, 2001
Product Specification
XILINX [ XILINX, INC ]
