R
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
The V
REF
pins within a bank are interconnected internally
and consequently only one V
REF
voltage can be used within
each bank. All V
REF
pins in the bank, however, must be con-
nected to the external voltage source for correct operation.
Within a bank, inputs that require V
REF
can be mixed with
those that do not. However, only one V
REF
voltage can be
used within a bank.
In Virtex-E, input buffers with LVTTL, LVCMOS2,
LVCMOS18, PCI33_3, PCI66_3 standards are supplied by
V
CCO
rather than V
CCINT
. For these standards, only input
and output buffers that have the same V
CCO
can be mixed
together.
The V
CCO
and V
REF
pins for each bank appear in the device
pin-out tables and diagrams. The diagrams also show the
bank affiliation of each I/O.
Within a given package, the number of V
REF
and V
CCO
pins
can vary depending on the size of device. In larger devices,
more I/O pins convert to V
REF
pins. Since these are always
a super set of the V
REF
pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device if necessary. All the V
REF
pins for the largest device
anticipated must be connected to the V
REF
voltage, and not
used for I/O.
In smaller devices, some V
CCO
pins used in larger devices
do not connect within the package. These unconnected pins
can be left unconnected externally, or they can be con-
nected to the V
CCO
voltage to permit migration to a larger
device, if necessary.
Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in
Each bank has
multiple V
CCO
pins, all of which must be connected to the
same voltage. This voltage is determined by the output
standards in use.
Bank 0
Bank 7
Bank 1
Bank 2
ds022_03_121799
GCLK3 GCLK2
VirtexE
Device
Bank 6
GCLK1 GCLK0
Bank 5
Bank 4
Bank 3
Figure 3:
Virtex-E I/O Banks
Within a bank, output standards can be mixed only if they
use the same V
CCO
. Compatible standards are shown in
GTL and GTL+ appear under all voltages because
their open-drain outputs do not depend on V
CCO
.
Table 2:
V
CCO
3.3 V
2.5 V
1.8 V
1.5 V
Compatible Output Standards
Compatible Standards
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
GTL+, LVPECL
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,
BLVDS, LVDS
LVCMOS18, GTL, GTL+
HSTL I, HSTL III, HSTL IV, GTL, GTL+
Configurable Logic Block
The basic building block of the Virtex-E CLB is the logic cell
(LC). An LC includes a 4-input function generator, carry
logic, and a storage element. The output from the function
generator in each LC drives both the CLB output and the D
input of the flip-flop. Each Virtex-E CLB contains four LCs,
organized in two similar slices, as shown in
shows a more detailed view of a single slice.
Some input standards require a user-supplied threshold
voltage, V
REF
. In this case, certain user-I/O pins are auto-
matically configured as inputs for the V
REF
voltage. Approx-
imately one in six of the I/O pins in the bank assume this
role.
DS025-2 (v2.1) July 17, 2002
1-800-255-7778
Module 2 of 4
3
XILINX [ XILINX, INC ]
