MT88E43B
Data Sheet
IN+
IN-
GS
VRef
CAP
TRIGin
TRIGRC
TRIGout
MODE
OSCin
OSCout
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
StD
INT
CD
DR
DATA
DCLK
FSKen
PWDN
IC
Figure 2 - Pin Connections
Pin Description
Pin #
1
2
3
4
5
6
7
Name
IN+
IN-
GS
V
Ref
CAP
Description
Non-inverting Input
of the internal opamp.
Inverting Input
of the internal opamp.
Gain Select (Output)
of internal opamp. The opamp’s gain should be set according to the
nominal Vdd of the application using the information in Figure 10.
Reference Voltage (Output).
Nominally V
DD
/2
. It is used to bias the input opamp.
Capacitor.
A 0.1
µF
decoupling capacitor should be connected across this pin and V
SS
.
TRIGin
Trigger Input.
Schmitt trigger buffer input. Used for line reversal and ring detection.
TRIGRC
Trigger RC (Open Drain Output/Schmitt Input).
Used to set the (RC) time interval from
TRIGin going low to TRIGout going high. An external resistor connected to V
DD
and capacitor
connected to V
SS
determine the duration of the (RC) time interval.
TRIGout
Trigger Out (CMOS Output).
Schmitt trigger buffer output. Used to indicate detection of line
reversal and/or ringing.
MODE
3-wire interface: Mode Select (CMOS Input).
When low, selects interface mode 0. When high,
selects interface mode 1. See pin 16 (DCLK) description to understand how MODE affects the
DCLK pin.
Oscillator Input.
A 3.579545 MHz crystal should be connected between this pin and OSCout. It
may also be driven directly from an external clock source.
8
9
10
11
12
13
14
OSCin
OSCout
Oscillator Output.
A 3.579545 MHz crystal should be connected between this pin and OSCin.
When OSCin is driven by an external clock, this pin should be left open.
V
SS
IC
Power Supply Ground.
Internal Connection.
Must be connected to V
SS
for normal operation.
PWDN
Power Down (Schmitt Input).
Active high. When high, the device consumes minimal power by
disabling all functionality except TRIGin, TRIGRC and TRIGout. Must be pulled low for device
operation.
FSKen
FSK Enable (CMOS Input).
Must be high for FSK demodulation. This pin should be set low to
prevent the FSK demodulator from reacting to extraneous signals (such as speech, alert signal
and DTMF which are all in the same frequency band as FSK).
DCLK
3-wire Interface: Data Clock (CMOS Input/Output).
In mode 0 (MODE pin low), this pin is an
output. In mode 1 (MODE pin high), this pin is an input.
15
16
2
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
