MT88E43
transfer is initiated by the MT88E43; in mode 1, data
transfer is initiated by the external microcontroller.
Mode 0
This mode is selected when the MODE pin is low. It
is the MT8841 compatible mode where data transfer
is initiated by the device.
In this mode, the MT88E43 receives the FSK signal,
demodulates it, and outputs the data directly to the
DATA pin (refer to Figure 14). For each received
stop and start bit sequence, the MT88E43 outputs a
fixed frequency clock string of 8 pulses at the DCLK
pin. Each clock rising edge occurs in the centre of
each DATA bit cell. DCLK is not generated for the
stop and start bits. Consequently, DCLK will clock
only valid data into a peripheral device such as a
serial to parallel shift register or a micro-controller.
The MT88E43 also outputs an end of word pulse
(data ready) on the DR pin. The data ready signal
indicates the reception of every 10-bit word
(including start and stop bits) sent from the network
to the TE/CPE. This DR signal can be used to
interrupt a micro-controller. DR can also cause a
serial to parallel converter to parallel load its data
into a microcontroller. The mode 0 data pin can also
be connected to a personal computer’s serial
communication port after converting from CMOS to
RS-232 voltage levels.
Mode 1
Interrupt
This mode is selected when the MODE pin is high. In
this mode, the microcontroller supplies read pulses
(DCLK) to shift the 8-bit data words out of the
MT88E43, onto the DATA pin. The MT88E43 asserts
DR to denote the word boundary and indicate to the
microprocessor that a new word has become
available (refer to Figure 16).
Internal to the MT88E43, the demodulated data bits
are sampled and stored. After the 8th bit, the word is
parallel loaded into an 8 bit shift register and DR
goes low. The shift register’s contents are shifted out
to the DATA pin on the supplied DCLK’s rising edge
in the order they were received.
If DCLK begins while DR is low, DR will return to high
upon the first DCLK. This feature allows the
associated interrupt (see section on "Interrupt") to be
cleared by the first read pulse. Otherwise DR is low for
half a nominal bit time (1/2400 sec).
After the last bit has been read, additional DCLKs
are ignored.
•
Carrier Detect
Preliminary Information
The carrier detector provides an indication of the
presence of a signal in the FSK frequency band. It
detects the presence of a signal of sufficient
amplitude at the output of the FSK bandpass filter.
The signal is qualified by a digital algorithm before
the CD output is set low to indicate carrier detection.
An 8ms hysteresis is provided to allow for
momentary signal drop out once CD has been
activated. CD is released when there is no activity at
the FSK bandpass filter output for 8 ms.
When CD is inactive (high), the raw output of the
demodulator is ignored by the data timing recovery
circuit (refer to Figure 1). In mode 0, the DATA pin is
forced high. No DCLK or DR signal is generated. In
mode 1, the internal shift register is not updated. No
DR is generated. If DCLK is clocked (in mode 1),
DATA is undefined.
Note that signals such as dual tone alert signal,
speech and DTMF tones also lie in the FSK
frequency band and the carrier detector may be
activated by these signals. The signals will be
demodulated and presented as data. To avoid false
data detection, the FSKen pin should be used to
disable the FSK demodulator when no FSK signal is
expected.
Ringing, on the other hand, does not pose a problem
as it is ignored by the carrier detector.
To facilitate interfacing with microcontrollers running
interrupt driven firmwear, an open drain interrupt
output INT is provided. INT is asserted when
TRIGout is low, StD is high, or DR is low. When INT
is asserted, these signals should be read (through an
input port of the microcontroller) to determine the
cause of the interrupt (TRIGout, StD or DR) so that
the appropriate response can be made.
When system power is first applied, TRIGout will be
low because capacitor C3 at TRIGRC (see Figure 3)
has no initial charge. This will result in an interrupt
upon power up. Also when system power is first
applied and the PWDN pin is low, an interrupt will
occur due to StD. Since there is no charge across
the capacitor at the St/GT pin in Figure 4, StD will be
high triggering an interrupt. The interrupts will not
clear until both capacitors are charged. The
microcontroller should ignore interrupt from these
sources on initial power up until there is sufficient
time to charge the capacitors.
5-60
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
