Data Sheet
It is possible to clear StD and its interrupt by
asserting PWDN immediately after system power up.
When PWDN is high, StD is low. PWDN will also
force both ESt and the comparator output low, Q2
will turn on so that the capacitor at the St/GT pin
charges up quickly (refer to Figure 4).
Power Down Mode
VRef and CAP Inputs
For
applications
requiring
reduced
power
consumption, the MT88E43 can be powered up only
when it is required, that is, upon detection of one of
three CLIP/CID call arrival indicators: line reversal,
ring burst and ringing.
The MT88E43 is powered down by asserting the
PWDN pin. In powerdown mode, the crystal
oscillator, opamp and all internal circuitry, except for
TRIGin, TRIGRC and TRIGout pins, are disabled.
The three TRIG pins are not affected by power down,
such that, the MT88E43 can still react to call arrival
indicators. The MT88E43 can be powered up by
grounding the PWDN pin.
Crystal Oscillator
The MT88E43 requires a 3.579545MHz crystal
oscillator as the master timing source.
MT88E43
can be D.C. coupled as shown, or the OSC1 input on
all devices can be driven from a CMOS buffer (dc
coupled) with the OSC2 outputs left unconnected.
To meet BT and Bellcore requirements for proper
tone detection the crystal must have a frequency
tolerance of 0.1%.
V
Ref
is the output of a low impedance voltage source
equal to V
DD/2
and is used to bias the input opamp. A
0.1µF capacitor is required between CAP and V
SS
to
eliminate noise on V
Ref.
MT88E43
OSC1
OSC2
MT88E43
OSC1
OSC2
MT88E43
OSC1
OSC2
3.579545 MHz
to the
next MT88E43
Figure 8 - Common Crystal Connection
The crystal specification is as follows:
Frequency:
Frequency tolerance:
Resonance mode:
Load capacitance:
Maximum series resistance:
Maximum drive level (mW):
e.g., CTS MP036S
3.579545 MHz
±0.1%(-40
o
C+85
o
C)
Parallel
18 pF
150 ohms
2 mW
Any number of MT88E43 devices can be connected
as shown in Figure 8 such that only one crystal is
required. The connection between OSC2 and OSC1
5-61
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
