MT89L80
Data Sheet
Stream
Address
Bits
Channel
Address
Bits
7
6
5
4
3
2
1
0
Bit
7-5*
Name
Stream
Address
Bits*
Channel
Address
Bits*
Description
The number expressed in binary notation on these 3 bits is the number of the ST-BUS
stream for the source of the connection. Bit 7 is the most significant bit. e.g., if bit 7 is 1,
bit 6 is 0 and bit 5 is 0, then the source of the connection is a channel on STi4.
The number expressed in binary notation on these 5 bits is the number of the channel
which is the source of the connection (The ST-BUS stream where the channel lies is
defined by bits 7, 6 and 5.). Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2
is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
4-0*
*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire
8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated
to define the source of the connection which is output on the channel and stream associated with this location.
Figure 6 - Connection Memory Low Bits
If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory High location function normally
(see Fig. 5). If bit 2 is 1, the associated ST-BUS output channel is in Message Mode; i.e., the byte in the
corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the
bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the ST-
BUS input stream and channel where the byte is to be found (see Fig. 6).
If the ODE pin is low, then all serial outputs are high-impedance. If it is high and bit 6 in the Control Register is 1,
then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the
Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output
stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5).
Bit 1 of each Connection Memory High location (see Fig. 5) is output on the CSTo pin once every frame. To allow for
delay in any external control circuitry the bit is output one channel before the corresponding channel on the ST-BUS
streams, and the bit for stream 0 is output first in the channel; e.g., bit 1’s for channel 9 of streams 0-7 are output
synchronously with ST-BUS channel 8 bits 7-0.
Applications
Use in a Simple Digital Switching System
Figs. 7 and 8 show how MT89L80s can be used with MT8964s to form a simple digital switching system. Fig. 7
shows the interface between the MT89L80s and the filter/codecs. Fig. 8 shows the position of these components in
an example architecture.
The MT8964 filter/codec in Fig. 7 receives and transmits digitized voice signals on the ST-BUS input D
R
, and ST-
BUS output D
X
, respectively. These signals are routed to the ST-BUS inputs and outputs on the top MT89L80,
which is used as a digital speech switch.
The MT8964 is controlled by the ST-BUS input D
C
originating from the bottom MT89L80, which generates the
appropriate signals from an output channel in Message Mode. This architecture optimizes the messaging capability
7
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
