MT89L80
Pin Description (continued)
Pin #
44
48
PLCC SSOP
14
15-17
19-21
22
23
24
25-27
29-33
34
35-39
41-43
44
15
16-18
20-22
23
24
26
27-29
31-35
1,
25,37
38-42
44-46
47
Name
C4i
A0-2
A3-5
DS
R/W
CS
D7-D5
D4-D0
V
SS
Description
Data Sheet
4.096 MHz Clock
(5 V-tolerant Input). ST-BUS bit cell boundaries lie on the alternate
falling edges of this clock.
Address 0-2 / Input Streams 8-10
(5 V-tolerant Input). These are the inputs for the
address lines on the microprocessor interface.
Address 3-5 / Input Streams 11-13
(5 V-tolerant Input). These are the inputs for the
address lines on the microprocessor interface.
Data Strobe
(5 V-tolerant Input). This is the input for the active high data strobe on the
microprocessor interface.
Read/Write
(5 V-tolerant Input). This is the input for the read/write signal on the
microprocessor interface - high for read, low for write.
Chip Select
(5 V-tolerant Input). This is the input for the active low chip select on the
microprocessor interface
Data Bus
(5 V-tolerant I/O): These are the bidirectional data pins on the
microprocessor interface.
Data Bus
(5 V-tolerant I/O): These are the bidirectional data pins on the
microprocessor interface.
Ground.
STo7-3 ST-BUS Outputs 7 to 3
(5 V-Tolerant Three-state Outputs). These are the pins for the
eight 2048 kbit/s ST-BUS output streams.
STo2-0 ST-BUS Outputs 2to 0
(5 V-Tolerant Three-state Outputs). These are the pins for the
eight 2048kbit/s ST-BUS output streams.
ODE
Output Drive Enable
(5 V-tolerant Input). If this input is held high, the STo0-STo7
output drivers function normally. If this input is low, the STo0-STo7 output drivers go into
their high impedance state.
NB:
Even when ODE is high, channels on the STo0-STo7
outputs can go high impedance under software control.
Control ST-BUS Output
(5 V-Tolerant Output). Each frame of 256 bits on this ST-BUS
output contains the values of bit 1 in the 256 locations of the Connection Memory High.
No Connection.
1
48
CSTo
NC
6, 18, 6, 19,
28, 40 30, 43
Functional Description
In recent years, there has been a trend in telephony towards digital switching, particularly in association with
software control. Simultaneously, there has been a trend in system architectures towards distributed processing or
multi-processor systems.
In accordance with these trends, Zarlink has devised the ST-BUS (Serial Telecom Bus). This bus architecture can
be used both in software-controlled digital voice and data switching, and for interprocessor communications. The
uses in switching and in interprocessor communications are completely integrated to allow for a simple general
purpose architecture appropriate for the systems of the future.
3
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
