ZL30116
Data Sheet
Normal (locked)
The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified
reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency
accuracy of the reference input. While in the normal mode, the DPLL’s clock and frame pulse outputs comply with
the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication
standards.
Holdover
When the DPLL operating in the normal mode loses its reference input, and no other qualified references are
available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data
collected while the DPLL was synchronized. The transition between normal and holdover modes is controlled by
the DPLL so that its initial frequency offset is better than 1 ppb which meets the requirement of Stratum 3E. The
frequency drift after this transition period is dependant on the frequency drift of the external master oscillator.
1.3 Ref and Sync Inputs
There are eight reference clock inputs (ref0 to ref7) available to both DPLL1 and DPLL2. The selected reference
input is used to synchronize the output clocks. Each of the DPLLs have independent reference selectors which can
be controlled using a built-in state machine or set in a manual mode.
DPLL2
ref7:0
DPLL1
sync2:0
Figure 3 - Reference and Sync Inputs
Each of the ref inputs accept a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz.
Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is
within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8 kHz
are also available.
2 kHz
8 kHz
16.384 MHz
19.44 MHz
38.88 MHz
77.76 MHz
64 kHz
1.544 MHz
2.048 MHz
6.48 MHz
8.192 MHz
Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
