ZL30116
Pin #
J3
Name
tms
I/O
Type
I
u
Description
Data Sheet
Test Mode Select (LVCMOS).
JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
DD
. If this pin is not used
then it should be left unconnected.
Oscillator Master Clock Input (LVCMOS).
This input accepts a 20 MHz
reference from a clock oscillator (TCXO, OCXO). The stability and accuracy of
the clock at this input determines the free-run accuracy and the long term
holdover stability of the output clocks.
Oscillator Master Clock Output (LVCMOS).
This pin must be left unconnected
when the osci pin is connected to a clock oscillator.
Internal Connection.
Connect to ground.
Master Clock
K4
osci
I
K5
osco
O
Miscellaneous
J2
H7
J6
G3
K6
F2
F3
D9
E4
G8
G9
J8
J9
H6
H8
E8
F4
A5
A8
C10
B7
B8
H2
IC
IC
NC
Internal Connection.
Leave unconnected.
No Connection.
Leave unconnected.
Power and Ground
V
DD
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Positive Supply Voltage.
+3.3V
DC
nominal.
V
CORE
AV
DD
Positive Supply Voltage.
+1.8V
DC
nominal.
Positive Analog Supply Voltage.
+3.3V
DC
nominal.
AV
CORE
Positive Analog Supply Voltage.
+1.8V
DC
nominal.
10
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
