ZL30116
Changes Summary
The following table captures the changes from the January 2006 issue.
Page
25-27
Item
Software Register Description
Change
Data Sheet
Changed the naming and description of the frame
pulse delay offset registers to clearly show that
they form a 22-bit register spread out over 3 8-bit
registers. The 22-bit register must be considered a
multi-byte register during a read or write operation.
This affects registers 0x40-0x42, 0x45-0x47, and
0x58-0x5A.
The following table captures the changes from the December 2005 issue.
Page
12
14
Item
1.1, “DPLL Features“
Table 2
Change
Added 14 Hz and 28 Hz to available loop
bandwidths for DPLL1
Removed the Custom frequencies from the auto-
detect table. Custom frequencies are
configurable for each reference.
6
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
