ZL38002
Pin Description (continued)
QSOP
Pin #
25
TQFP
Pin #
27
Name
F0i
Description
Data Sheet
Frame Pulse (Input).
In ST-BUS (or GCI) operation, this is an active-low
(or active-high) frame alignment pulse, respectively. SSI operation is
enabled by connecting this pin to Vss.
26
29
BCLK/C4i
Bit Clock/ST-BUS Clock (Input).
In SSI operation, BCLK pin is a 128 kHz
to 4.096 MHz bit clock. This clock must be synchronous with ENA1 and
ENA2 enable strobes.
In ST-BUS or GCI operation, C4i pin must be connected to the 4.096 MHz
(C4) system clock.
IC
VSS2
VDD2
VSS
MCLK2
IC
NC
Internal Connection (Input).
Tie to Vss.
Digital Ground (Input).
Nominally 0 volts.
Positive Power Supply (Input).
Nominally 3.3 volts (tie together with
VDD).
Digital Ground (Input).
Nominally 0 volts (tie together with VSS2).
Master Clock (Input).
Nominal 20 MHz master clock (tie together with
MCLK).
Internal Connection (Input).
Tie to Vss.
No Connect (Output).
This pin should be left unconnected.
27, 28
29
30
31
33
34,35,36
15, 16, 21,
32
30, 31
33
34
35
38
39, 40, 41
1, 4, 10, 12,
14, 15, 18,
20, 22, 25,
28, 32, 36,
37, 42, 44
5
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
