ZL38004
ZL38004
Analog Clock Select
Analog Clock
Buffer
C0/1_BFo+
C0/1_ADCi-
C0/1_ADCi+
C0/1_BFo-
BIAS_VCM
BIAS_RF+
BIAS_RF-
Antialiasing
Filter
Analog
∆Σ
Modulator
3.0720 MHz
2.8224 MHz
Digital LP
Decimation
Filter
CODEC
PDM
Loopback
16
Data Sheet
ADCout
[15:0]
Bias
Generation
16
C0/1_DACo+
C0/1_DACo-
Reconstruction
Filter & Driver
CODEC
PDM
Loopback
Digital
∆Σ
Modulator
Analog Clock
Digital LP
Interpolation
Filter
16 DACin
[15:0]
CODEC
Parallel
Loopback
Figure 2 - CODEC Block Diagram
4.0
PCM / I
2
S Ports
The PCM ports 0 and 1 support data communication between an external peripheral device and the ZL38004 DSP
Core using separate input (P0/1PCMi) and output (P0/1PCMo) serial streams with TDM (i.e., ST-BUS, GCI or
McBSP) or SSI interface timing in both master or slave timing modes. Both PCM Ports 0 and 1 support the same
functionality and modes of operation.
PCM Port 1 pin functions are shared with the I
2
S Port pin functions. The I
2
S (Inter-IC Sound) port and PCM Port
One share the same physical pins of the ZL38004. Selection of either I
2
S port operation or PCM Port One operation
is done through the Port One PCM/I
2
S Select Register. See firmware manual.
The I
2
S port can be used to connect external Analog-to-Digital Converters or CODECs to the internal DSP. This
port can operate in master mode, where the ZL38004 is the source of the port clocks, or slave mode, where the bit
and sampling clocks (I
2
S_SCK and I
2
S_ LRCK) are inputs to the ZL38004. In I
2
S port master mode the clock signal
at output pin I
2
S_LRCK is the sampling frequency (f
S
), the clock signal at output I
2
S_SCK is 32 x f
S
, and the clock
signal at output I
2
S_MCLK is 256 x f
S
. In I
2
S port slave mode the relationship between the clock signal at input pin
I
2
S_LRCK and the clock signal at input I
2
S_SCK must be 32 x f
S
. In slave mode the 256 x f
S
relationship between
f
S
and the I
2
S_MCLK is not mandatory, and the I
2
S_MCLK output pin will be in a high impedance state.
Access to the control and status registers associated with these ports is through the Slave SPI port or UART.
6
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
