ZL50012
Pin Description (continued)
LQFP Pin
Number
115
LBGA Ball
Number
M12
Name
R/W
Description
Data Sheet
Read/Write (5 V Tolerant Input):
This input controls the
direction of the data bus lines (D0-D15) during a
microprocessor access.
Data Strobe (5 V Tolerant Input):
This active low input works
in conjunction with CS to enable the microprocessor port read
and write operations.
Address 0 - 11 (5 V Tolerant Inputs):
These pins form the 12-
bit address bus to the internal memories and registers.
116
H10
DS
117, 118
123 - 125
128 - 130
131 - 134
137 - 139
140 - 142
143, 144
147 - 149
150 - 152
153, 154
M10, M11
L10, L11, K11
K10, L12, K12
J11, J10, J9,
J12
H9, G9, H11
H12, G12, G11
G10, F10
D10, E10, F11
F12, E12, E11
D12, C12
A0 - A1
A2 - A4
A5 - A7
A8 - A11
STi0 - 2
STi3 - 5
STi6 - 7
STi8 - 10
STi11- 13
STi14 - 15
Serial Input Streams 0 to 15 (5 V Tolerant Inputs):
The data
rate of these input streams can be selected independently
using the stream input control registers. In the 2.048 Mb/s
mode, these pins accept serial TDM data streams at
2.048 Mb/s with 32 channels per stream. In the 4.096 Mb/s
mode, these pins accept serial TDM data streams at
4.096 Mb/s with 64 channels per stream. In the 8.192 Mb/s
mode, these pins accept serial TDM data streams at
8.192 Mb/s with 128 channels per stream.
Unused serial input pins are required to connect to either Vdd
or ground, through an external pull-up resistors or external pull-
down resistor.
Device Reset (5 V Tolerant Input):
This input (active LOW)
puts the device in its reset state that disables the STo0 - 15
drivers and drives the STOHZ 0 - 15 outputs to high. It also
clears the device registers and internal counters. To ensure
proper reset action, the reset pin must be low for longer than
1 ms. Upon releasing the reset signal to the device, the first
microprocessor access can take place after 600
µs
due to the
time required to stabilize the APLL block from the power down
state.
Test Serial Data Out (3 V Tolerant Three-state Output):
JTAG serial data is output on this pin on the falling edge of
TCK. This pin is held in high impedance state when JTAG is not
enabled.
No Connection Pins.
These pins are not connected to the
device internally.
157
D11
RESET
158
C11
TDo
1, 2, 29,
39 - 42,
79 - 82,
119 - 122,
159, 160
C5, C6
NC
15
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
