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ZL50012QCG1 参数 Datasheet PDF下载

ZL50012QCG1图片预览
型号: ZL50012QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 灵活的512路数字开关 [Flexible 512-ch Digital Switch]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 66 页 / 563 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50012
Pin Description
LQFP Pin
Number
10, 23, 33,
43, 48, 58,
68, 78, 92,
102, 113,
127, 136,
146, 156
9, 18, 21,
32, 38, 47,
57, 67, 77,
91, 101,
112, 126,
135, 145,
155
3
LBGA Ball
Number
D5, D6, D7
E9
F4, F9
G4
H4
J6, J7, J8
D4, D9
E5, E6, E7, E8
F5, F6, F7, F8
G5, G6, G7,
G8
H5, H6, H7, H8
J4
B12
Name
V
DD
Description
Power Supply for the device:
+3.3 V
Data Sheet
V
ss
(GND)
Ground.
TMS
Test Mode Select (3.3 V Tolerant Input with internal pull-
up):
JTAG signal that controls the state transitions of the TAP
controller. This pin is pulled high by an internal pull-up resistor
when it is not driven.
Test Clock (5 V Tolerant Input):
Provides the clock to the
JTAG test logic.
Test Reset (3.3 V Tolerant Input with internal pull-up):
Asynchronously initializes the JTAG TAP controller by putting it
in the Test-Logic-Reset state. This pin should be pulsed low
during power-up to ensure that the device is in the normal
functional mode. When JTAG is not being used, this pin should
be pulled low during normal operation.
Test Serial Data In (3.3 V Tolerant Input with internal pull-
up):
JTAG serial test instructions and data are shifted in on this
pin. This pin is pulled high by an internal pull-up resistor when it
is not driven.
ST-BUS Frame Pulse Input (5 V Tolerant Input):
This pin
accepts the frame pulse which stays low for 61 ns, 122 ns or
244 ns at the frame boundary. The frame pulse associating
with the highest input data rate has to be applied to this pin.
The frame pulse frequency is 8 kHz. The device also accepts
positive frame pulse if the FPINP bit is high in the Internal
Mode Selection register.
ST-BUS Clock Input (5 V Tolerant Input):
This pin accepts a
4.096 MHz, 8.192 MHz or 16.384 MHz clock. The input clock
frequency has to be equal to or greater than twice of the
highest input data rate. The clock falling edge defines the input
frame boundary. The device also allows the clock rising edge to
define the frame boundary by programming the CKINP bit in
the Internal Mode Selection register.
4
5
A12
B11
TCK
TRST
6
A11
TDi
7
B10
FPi
8
A10
CKi
12
Zarlink Semiconductor Inc.