ZL50016
Enhanced 1 K Digital Switch
Data Sheet
Features
•
1024 channel x 1024 channel non-blocking digital
Time Division Multiplex (TDM) switch at
4.096 Mbps, 8.192 Mbps and 16.384 Mbps or
using a combination of ports running at
2.048 Mbps, 4.096 Mbps, 8.192 Mbps and
16.384 Mbps
16 serial TDM input, 16 serial TDM output
streams
Output streams can be configured as bi-
directional for connection to backplanes
Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
Per-stream input and output data rate conversion
selection at 2.048 Mbps, 4.096 Mbps,
8.192 Mbps or 16.384 Mbps. Input and output
data rates can differ
Per-stream high impedance control outputs
(STOHZ) for 8 output streams
•
•
•
•
•
•
Ordering Information
ZL50016GAC
ZL50016QCC
ZL50015QCG1
ZL50016GAG2
256 Ball PBGA
256 Lead LQFP
256 Lead LQFP*
256 Ball PBGA**
Trays
Trays
Trays, Bake &
Drypack
Trays, Bake &
Drypack
November 2006
•
•
•
•
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
-40°C to +85°C
Per-stream input bit delay with flexible sampling
point selection
Per-stream output bit and fractional bit
advancement
Per-channel ITU-T G.711 PCM A-Law/µ-Law
Translation
Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
Input frame pulses:61 ns, 122 ns, 244 ns
Four frame pulse and four reference clock outputs
•
V
DD_CORE
V
DD_IO
V
DD_COREA
V
DD_IOA
V
SS
RESET
ODE
STi[15:0]
FPi
CKi
MODE_4M0
MODE_4M1
S/P Converter
Data Memory
P/S Converter
STio[15:0]
Input Timing
Connection Memory
Output HiZ
Control
STOHZ[7:0]
Output Timing
FPo[3:0]
CKo[3:0]
FPo_OFF[2:0]
Internal Registers &
Microprocessor Interface
Test Port
TDi
D[15:0]
DS_RD
A[13:0]
R/W_WR
Figure 1 - ZL50016 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
MOT_INTEL
DTA_RDY
TRST
TMS
TCK
TDo
CS
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
