ZL50031
Data Sheet
Pin Description (continued)
256 Pin HQFP
Name
Description
57 to 54
LREF0 - 3
Local Reference (5 V Tolerant Inputs). These pins accept 8 kHz,
1.544 MHz or 2.048 MHz local timing reference.
66
65
NREFo
Network Reference Output (Output). Any local reference can be switched
to this output. The output data rate can be either the same as the selected
reference input data rate or divided to be 8 kHz.
PRI_LOS
Primary Reference Lost (5 V Tolerant Input). When this signal is high, it
indicates that PRIMARY REFERENCE is not valid. Combined with
SEC_LOS input, this input pin is used in the External Reference Switching
Mode of the DPLL.
64
63
SEC_LOS
C32/64o
Secondary Reference Lost (5 V Tolerant Input). When this signal is high,
it indicates that SECONDARY REFERENCE is not valid. Combined with the
PRI_LOS input, this input pin is used in the External Reference Switching
Mode of the DPLL.
C32/64o Clock (5 V Tolerant Output). A 32.768 MHz output clock when the
DPLL Clock Monitor register bit (CKM) is low. A 65.536 MHz clock when the
DPLL Clock Monitor register bit (CKM) is high.
58
60
C1M5o
C1.5o Clock (5 V Tolerant Output). A 1.544 MHz output clock.
ST_FPo0
ST-BUS Frame Pulse Output (5 V Tolerant Output). The width of this
output ST-BUS frame pulse can be 244 ns, 122 ns or 61 ns. The frequency
is 8 kHz.
61
30
ST_CKo0
ST_FPo1
ST-BUS Clock Output (5 V Tolerant Output). The frequency of this output
ST-BUS clock can be 4.096 MHz, 8.192 MHz or 16.384 MHz.
ST-BUS Frame Pulse Output (5 V Tolerant Output). The width of this
output ST-BUS frame pulse can be 244 ns, 122 ns or 61 ns. The frequency
is 8 kHz.
31
ST_CKo1
CS
ST-BUS Clock Output (5 V Tolerant Output). The frequency of this output
ST-BUS clock can be 4.096 MHz, 8.192 MHz or 16.384 MHz.
254
255
256
Chip Select (5 V Tolerant Input). This active low input is used by the
microprocessor to access the microport.
DS
Data Strobe (5 V Tolerant Input). This active low input works in conjunction
with CS to initiate the read and write cycles.
R/W
Read/Write (5 V Tolerant Input). This input controls the direction of the data
bus lines (D0 - D15) during the microprocessor access.
16 to 9
and
A0 - A13
Address 0 - 13 (5 V Tolerant Inputs). These are the address lines to the
internal memories and registers.
6 to 1
251 to 244
and
D0 - D15
DTA
Data Bus 0 - 15 (5 V Tolerant I/Os). These pins form the 16-bit data bus of
the microport.
241 to 234
233
Data Transfer Acknowledge (5 V Tolerant Output). This active low output
indicates that a data bus transfer is completed. A pull-up resistor is required
to hold a high level.
10
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