ZL50110/11/12/14
Description
Data Sheet
The ZL50110/11/12/14 family of CESoP processors are highly functional TDM to Packet bridging devices. The
ZL50110/11/12/14 provides both structured and unstructured circuit emulation services over packet (CESoP) for up
to 32 T1, 32 E1 and 8 J2 streams across a packet network based on MPLS, IP or Ethernet. The ZL50111 also
supports unstructured T3 and E3 streams.
The circuit emulation features in the ZL50110/11/12/14 family supports the ITU Recommendations Y.1413 and
Y.1453, as well as the CESoP standards from the Metro Ethernet Forum (MEF) and MPLS and Frame Relay
Alliance. The ZL50110/11/14 also supports IETF RFC4553 and RFC5086.
The ZL50110/11/12/14 provides up to triple 100 Mbps MII ports or dual redundant 1000 Mbps GMII/TBI ports.
The ZL50110/11/12/14 incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing
the frequency of the source clock to be faithfully generated at the destination, enabling greater system performance
and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery
schemes are included, allowing the customer to choose the correct scheme for the application. An externally
supplied clock may also be used to drive the TDM interface of the ZL50110/11/12/14.
The ZL50110/11/12/14 incur very low latency for the data flow, thereby increasing QoS when carrying voice
services across the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of
less than 10 ms, does not require expensive processing such as compression and echo cancellation.
The ZL50110/11/12/14 is capable of assembling user-defined packets of TDM traffic from the TDM interface and
transmitting them out the packet interfaces using a variety of protocols. The ZL50110/11/12/14 supports a range of
different packet switched networks, including Ethernet VLANs, IP and MPLS.
The ZL50110/11/12/14 can support up to 4 protocol stacks at the same time, provided that each protocol stack can
be uniquely identified by a mask & match approach.
Packets received from the packet interfaces are parsed to determine the egress destination, and are appropriately
queued to the TDM interface, they can also be forwarded to the host interface, or back toward the packet interface.
Packets queued to the TDM interface can be re-ordered based on sequence number, and lost packets filled in to
maintain timing integrity.
The ZL50110/11/12/14 family includes sufficient on-chip memory that external memory is not required in most
applications. This reduces system costs and simplifies the design. For applications that do require more memory
(e.g., high stream count or high latency), the device supports up to 8 Mbytes of SSRAM.
A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor.
This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI
that runs on a Windows PC.
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
