ZL50234
Data Sheet
Pin Description (continued)
PIN #
PIN
Description
Name
100 PIN
LQFP
208-Ball LBGA
Rin
F0i
B7
61
Receive PCM Signal Input (Input). Port 1 TDM data input
streams. Rin pin receives serial TDM data streams at
2.048 Mbps with 8 channels per stream.
B5
62
Frame Pulse (Input). This input accepts and automatically
identifies frame synchronization signals formatted according to
ST-BUS or GCI interface specifications.
A4
G2
63
90
Serial Clock (Input). 4.096 MHz serial clock for shifting data
C4i
in/out on the serial streams (Rin, Sin, Rout, Sout).
MCLK
Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock
input. May be connected to an asynchronous (relative to frame
signal) clock source.
Fsel
H2
K3
92
Frequency select (Input). This input selects the Master Clock
frequency operation. When Fsel pin is low, nominal 20 MHz
Master Clock input must be applied. When Fsel pin is high,
nominal 10 MHz Master Clock input must be applied.
PLLVss1
PLLVss2
97, 95
PLL Ground. Must be connected to VSS
PLLVDD
TMS
K4
96
1
PLL Power Supply. Must be connected to VDD2 = 1.8 V
M2
Test Mode Select (3.3 V Input). JTAG signal that controls the
state transitions of the TAP controller. This pin is pulled high by
an internal pull-up when not driven.
TDI
M1
N1
2
3
Test Serial Data In (3.3 V Input). JTAG serial test instructions
and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
TDO
Test Serial Data Out (Output). JTAG serial data is output on this
pin on the falling edge of TCK. This pin is held in high impedance
state when JTAG scan is not enabled.
TCK
P1
N2
4
6
Test Clock (3.3 V Input). Provides the clock to the JTAG test
logic.
Test Reset (3.3 V Input). Asynchronously initializes the JTAG
TAP controller by putting it in the Test-Logic-Reset state. This pin
should be pulsed low on power-up or held low, to ensure that the
ZL50234 is in the normal functional mode. This pin is pulled by
an internal pull-down when not driven.
TRST
R3
8
Device Reset (Schmitt Trigger Input). An active low resets the
device and puts the ZL50234 into a low-power stand-by mode.
When the RESET pin is returned to logic high and a clock is
applied to the MCLK pin, the device will automatically execute
initialization routines, which preset all the Main Control and
Status Registers to their default power-up values.
RESET
9
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
