ZL50404
Data Sheet
Processor
Serial Out
Serial In
Strobe Interrupt
Synchronous Serial Interface
3-bit Address Bus
16-bit Data Bus
INT CS W R
Address
I/O Data MUX
Index Reg 1
(Addr = 1)
Index Reg 0
(Addr = 0)
Config Data
Reg
(Addr = 2)
CPU Frame Reg
(Addr = 3)
Command/
Status Reg
(Addr = 4)
Interrupt
Reg
(Addr = 5)
Control
Command 1 Reg
(Addr = 6)
Control
Command 2
Reg
(Addr = 7)
16-bit Address
8-bit Data Bus
8/16-bit Data Bus
8/16-bit Data Bus
Internal
Registers
Inderect
Access
CPU frame
Transmit
CPU frame
Receive FIFO
FIFO
Control
Control Command 1
Command 1Transmit
Receive
FIFO
FIFO
Control
Command 2
Transmit
FIFO
Interrupt
Figure 3 - Overview of the SSI Interface
3.1
3.1.1
Register Configuration, Frame Transmission, and Frame Reception
Register Configuration
The ZL50404 has many programmable parameters, covering such functions as QoS weights, VLAN control, and
port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters.
The parameters are contained in 8-bit configuration registers. The device allows indirect access to these registers,
as follows:
•
In serial mode, the address, command and data are shifted in serially. To access the configuration registers,
only one “index” register (addresses 000b) needs to be written with the configuration register address. The
desired data can be written into or read from the “data” register (address 010b).
• For example, if “XX” is required to be written to register “YY”, a write of “YY” is required to write to
address “000b” (Index register). Then, a write of “XX” is required to write to address “010b” (Data
Register). This completes the register write and register “YY” will contain the value of “XX”.
To indirectly configure the register addressed by the index register, a “data” register (address 010b) must be
written with the desired 8-bit data.
•
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