ZL50404
•
Data Sheet
The ZL50404 supports special register-write in serial mode. This allows CPU to write to two consecutive
configuration registers in a single write operation. By writing to bit[14] of configuration register address,
CPU can write 16-bit data to address 010b. Lower 8 bit of data is for the address specified in index
register and upper 8 bit of data is for the address + 1.
14
SP
W
13
12
11
12 Bit Register Address
0
15
INC
R/W
Reserved
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Similarly, to read the value in the register addressed by the index register, the “data” register can now simply
be read.
The ZL50404 supports an incremental read/write. If CPU requires to read or write to the configuration
registers incrementally, CPU only has to write to index register once with the MSB of configuration register
address set and then CPU can continuously reading or writing to “data” register (010b).
In summary, access to the many internal registers is carried out simply by directly accessing only two registers –
one register to indicate the index of the desired parameter, and one register to read or write a value. Of course,
because there is only one bus master, there can never be any conflict between reading and writing the
configuration registers.
3.1.2
Rx/Tx of Standard Ethernet Frames
In serial only mode, the Ethernet frame is transmitted and received through the CPU interface. There is no ability to
send/receive Ethernet frames in unmanaged mode.
To transmit a frame from the CPU in serial only mode:
•
•
The CPU writes to the “data frame” register (address 011) with the frame size, destination port number, and
frame status. After writing all the transmitting status bytes, it then writes the data it wants to transmit
(minimum 64 bytes).
The ZL50404 forwards the Ethernet frame to the desired destination port, no longer distinguishing the fact
that the frame originated from the CPU.
The CPU receives an interrupt when an Ethernet frame is available to be received.
Frame information arrives first in the data frame register. This includes source port number, frame size, and
VLAN tag.
The actual data follows the frame information. The CPU uses the frame size information to read the frame
out.
To receive a frame into the CPU in serial only mode:
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•
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In summary, in serial only mode, receiving and transmitting frames to and from the CPU is a simple process that
uses one direct access register only.The details of sending an Ethernet Frame via the CPU interface is described in
the Processor Interface Application Note, ZLAN-26.
Although there is the ability to Tx/Rx Ethernet Frames via the serial interface in lightly managed mode, the ZL50404
is not meant to be used in a fully managed system. The speed of the serial interface limits management capability.
For example, if the system is trying to implement port security, it would require a faster interface between the CPU
and the ZL50404, such as the 8/16-bit interface or the serial + MII interface found on the managed device.
3.1.3
Control Frames
In addition to standard Ethernet frames described in the preceding section, the CPU is also called upon to handle
special “Control frames,” generated by the ZL50404 and sent to the CPU. These proprietary frames are related to
such tasks as statistics collection, MAC address learning, and aging, etc… All Control frames are up to 40 bytes
long. Transmitting and receiving these frames is similar to transmitting and receiving Ethernet frames, except that
the register accessed is the “Control frame data” register (address 111).
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