ZL50404
13.0
13.1
Data Sheet
Register Definition
ZL50404 Register Description
CPU Addr
(Hex)
I²C
Addr
(Hex)
Register
Description
R/W
Default
Notes
0. ETHERNET Port Control Registers (Substitute [n] with Port number (0..3,8,9))
ECR1Pn
ECR2Pn
ECR3Pn
ECR4Pn
BUF_LIMIT
FCC
Port Control Register 1 for
Port n
Port Control Register 2 for
Port n
Port Control Register 3 for
Port n
Port Control Register 4 for
Port n
Frame Buffer Limit
Flow Control Grant Period
000+2n
001+2n
080+2n
081+2n
036
037
R/W
R/W
R/W
R/W
R/W
R/W
000+n
00A+n
014+n
01E+n
NA
NA
0C0
000
000
018
040
003
1. VLAN Control Registers (Substitute [n] with Port number (0..3,8,9))
AVTCL
AVTCH
PVMAPn_0
PVMAPn_1
PVMAPn_3
PVMODE
VLAN Type Code Register
Low
VLAN Type Code Register
High
Port n Configuration
Register 0
Port n Configuration
Register 1
Port n Configuration
Register 3
VLAN Operating Mode
100
101
102+4n
103+4n
105+4n
170
R/W
R/W
R/W
R/W
R/W
R/W
028
029
02A+n
034+n
03E+n
048
000
081
0FF
0FF
000
000
2. TRUNK Control Registers (Substitute [n] with Trunk Group number (0..7))
TRUNKn
TRUNKn_HASH10
TRUNKn_HASH32
TRUNKn_HASH54
TRUNKn_HASH76
MULTICAST_HASHn-0
Trunk Group n
Trunk Group n Hash 10
Destination Port
Trunk Group n Hash 32
Destination Port
Trunk Group n Hash 54
Destination Port
Trunk Group n Hash 76
Destination Port
Multicast hash result n
mask byte 0
200+n
208+4n
209+4n
20A+4n
20B+4n
228+2n
R/W
R/W
R/W
R/W
R/W
R/W
NA
NA
NA
NA
NA
NA
000
000
000
000
000
0FF
Table 12 - Register Description
52
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
