ZL50404
Data Sheet
I²C
Addr
(Hex)
CPU Addr
Register
Description
R/W
Default
Notes
(Hex)
MCC
Multicast Congestion
Control
511
R/W
R/W
069
006
003
MCCTH
Multicast Congestion
Threshold
512
NA
RDRC0
WRED Drop Rate Control 0
WRED Drop Rate Control 1
WRED Drop Rate Control 2
Share FCB Size
513
514
515
518
519
51A
51B
530
531
532
533
540
541
542
543
550+n
558
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
090
091
NA
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
RDRC1
RDRC2
SFCB
074
075
076
077
056
057
058
05C
059
05A
05B
05D
0B3+n
0BB
C1RS
Class 1 Reserve Size
Class 2 Reserve Size
Class 3 Reserve Size
VLAN Priority Map Low
VLAN Priority Map Middle
VLAN Priority Map High
VLAN Discard Map
C2RS
C3RS
AVPML
AVPMM
AVPMH
AVDM
TOSPML
TOSPMM
TOSPMH
TOSDML
USER_PROTOCOL_n
TOS Priority Map Low
TOS Priority Map Middle
TOS Priority Map High
TOS Discard Map
User Define Protocol n
(n=0..7)
USER_PROTOCOL_
FORCE_DISCARD
User Define Protocol 0 To 7
Force Discard Enable
WLPP10
WLPP32
WLPP54
WLPP76
WLPE
Well Known Logic Port 0
and 1 Priority
560
561
562
563
564
565
R/W
R/W
R/W
R/W
R/W
R/W
0A8
0A9
0AA
0AB
0AC
0AD
000
000
000
000
000
000
Well Known Logic Port 2
and 3 Priority
Well Known Logic Port 4
and 5 Priority
Well Known Logic Port 6
and 7 Priority
Well Known Logic Port 0 To
7 Enable
WLPFD
Well Known Logic Port 0 To
7 Force Discard Enable
Table 12 - Register Description (continued)
54
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
