ZL50404
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When the CPU reads this register:
Bit [0]:
Control Frame receive buffer ready, CPU can write a new frame
1 – CPU can write a new control command 1
0 – CPU has to wait until this bit is 1 to write a new control command 1
Control Frame transmit buffer1 ready for CPU to read
1 – CPU can read a new control command 1
0 – CPU has to wait until this bit is 1 to read a new control command
Control Frame transmit buffer2 ready for CPU to read
1 – CPU can read a new control command 1
0 – CPU has to wait until this bit is 1 to read a new control command
Transmit FIFO has data for CPU to read (TXFIFO_RDY)
Receive FIFO has space for incoming CPU frame (RXFIFO_SPOK)
Transmit FIFO End Of Frame (TXFIFO_EOF)
Reserved
Data Sheet
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [7:6]:
13.2.5
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Interrupt Register
Interrupt sources (8 bits)
Address = 5 (read/write)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [6:3]:
Bit [7]:
CPU frame interrupt
Control Frame 1 interrupt. Control Frame receive buffer1 has data for CPU to read
Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU to read
Reserved
Device Timeout Detected interrupt
Note: This bit is not self-cleared. After reading, the CPU has to clear the bit writing 0 to it.
13.2.6
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Control Command Frame Buffer1 Access Register
CPU transmit/receive control frames (16 bits)
Address = 6 (read/write)
When CPU writes to this register:
Data is written to the Control Command Frame Receive Buffer
When CPU reads this register:
Data is read from the Control Command Frame Transmit Buffer1
13.2.7
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Control Command Frame Buffer2 Access Register
CPU receive control frames (16 bits)
Address = 7 (read only)
When CPU reads this register:
Data is read from the Control Command Frame Transmit Buffer2
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