ZL50404
Data Sheet
I²C
Addr
(Hex)
CPU Addr
Register
Description
MASK Timeout 2
R/W
Default
Notes
(Hex)
MASK2
MASK3
MASK4
E12
E13
R/W
R/W
R/W
RO
0F8
0F9
0FA
NA
000
000
000
NA
MASK Timeout 3
MASK Timeout 4
E14
BOOTSTRAP[2:0]
PRTFSMSTn
BOOTSTRAP Read Back
E80-E82
E90+n
Ethernet Port n Status
Read Back
RO
NA
NA
(n=0..3,8,
9)
PRTQOSSTn
PRTQOSST8A
PRTQOSST8B
PRTQOSST9A
PRTQUSST9B
RMAC Port n QOS and
Queue Status
EA0+n
EA8
RO
RO
RO
RO
RO
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
(n=0..3)
CPU Port QOS and Queue
Status A
CPU Port QOS and Queue
Status B
EA9
MMAC Port QOS and
Queue Status A
EAA
EAB
MMAC Port QOS and
Queue Status B
CLASSQOSST
PRTINTCTR
QMCTRLn
Class Buffer Status
EAC
EAD
RO
R/W
R/W
NA
NA
NA
NA
000
000
Buffer Interrupt Status
Ports Queue Control Status
EB0+n
(n=0..3,8,
9)
QCTRL
Ports Queue Control
Memory bist result
Memory bist result
Memory control
EBA
EBB
EBC
EBD
EC0
EC1
EC2
EC3
EC4
EC5
EC6
R/W
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
000
NA
BMBISTR0
BMBISTR1
NA
BMControl
00F
000
000
000
000
000
000
006
BUFF_RST
Buffer Reset Pool
FCBHEADPTR0
FCB_HEAD_PTR1
FCB_TAIL_PTR0
FCB_TAIL_PTR1
FCB_NUM0
FCB_NUM1
FCB Head Pointer [7:0]
FCB Head Pointer [15:8]
FCB Tail Pointer [7:0]
FCB Tail Pointer [15:8]
FCB Number [7:0]
FCB Init Start and FCB
Number [14:8]
BM_RLSFF_CTRL
BM_RLSFF_INFO0
BM_RLSFF_INFO1
Read control register
Bm_rlsfifo_info[7:0]
Bm_rlsfifo_info[15:8]
EC7
EC8
EC9
R/W
RO
RO
NA
NA
NA
000
NA
NA
Table 12 - Register Description (continued)
58
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
