eZ80F92/eZ80F93
Product Specification
232
External I/O Read Timing
nal transition timing is independent of the particular bus mode employed (eZ80, Z80,
Intel
TM
, or Motorola).
T
CLK
X
IN
T
1
ADDR[23:0]
T
3
DATA[7:0]
(input)
T
5
CSx
T
7
IORQ
T
9
RD
T
10
T
8
T
6
T
4
T
2
Figure 59.External I/O Read Timing
Table 152. External I/O Read Timing
Delay (ns)
Parameter
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
8
T
9
T
10
Abbreviation
Clock Rise to ADDR Valid Delay
Clock Rise to ADDR Hold Time
Input DATA Valid to Clock Rise Setup Time
Clock Rise to DATA Hold Time
Clock Rise to CSx Assertion Delay
Clock Rise to CSx Deassertion Delay
Clock Rise to IORQ Assertion Delay
Clock Rise to IORQ Deassertion Delay
Clock Rise to RD Assertion Delay
Clock Rise to RD Deassertion Delay
Min
—
2.0
1.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
Max
13
—
—
—
19.0
18.0
16.0
16.0
16.0
16.0
PS015309-1004
PRELIMINARY
Electrical Characteristics
ZILOG [ ZILOG, INC. ]
