eZ80L92 MCU
Product Specification
214
Table 133. GPIO Port Output Timing
20 MHz (ns)
Parameter
T
1
T
2
Abbreviation
Clock Rise to Port Output Valid Delay
Clock Rise to Port Output Hold Time
Min
—
2.0
Max
9.3
—
50 MHz (ns)
Min
—
2.0
Max
9.3
—
External Bus Acknowledge Timing
Table 134. Bus Acknowledge Timing
20 MHz (ns)
Parameter
T
1
T
2
Abbreviation
Clock Rise to BUSACK Assertion Delay
Clock Rise to BUSACK Deassertion Delay
Min
2.8
2.5
Max
9.3
6.5
50 MHz (ns)
Min
2.8
2.5
Max
9.3
6.5
External System Clock Driver (PHI) Timing
peripherals to synchronize with the internal system clock driver on the eZ80L92.
Table 135. PHI System Clock Timing
20 MHz (ns)
Parameter
T
1
T
2
Abbreviation
Clock Rise to PHI Rise
Clock Fall to PHI Fall
Min
1.6
1.8
Max
4.6
4.3
50 MHz (ns)
Min
1.6
1.8
Max
4.6
4.3
PS013012-1004
PRELIMINARY
AC Characteristics
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