Z8 Encore! XP
®
4K Series
Product Specification
56
Table 35. Interrupt Request 1 Register (IRQ1)
BITS
FIELD
RESET
R/W
ADDR
7
PA7VI
0
R/W
6
PA6CI
0
R/W
5
PA5I
0
R/W
4
PA4I
0
R/W
FC3H
3
PA3I
0
R/W
2
PA2I
0
R/W
1
PA1I
0
R/W
0
PA0I
0
R/W
PA7VI—Port A7 or LVD Interrupt Request
0 = No interrupt request is pending for GPIO Port A or LVD.
1 = An interrupt request from GPIO Port A or LVD.
PA6CI—Port A6 or Comparator Interrupt Request
0 = No interrupt request is pending for GPIO Port A or Comparator.
1 = An interrupt request from GPIO Port A or Comparator.
PAxI—Port A Pin
x
Interrupt Request
0 = No interrupt request is pending for GPIO Port A pin
x.
1 = An interrupt request from GPIO Port A pin
x
is awaiting service.
where
x
indicates the specific GPIO Port pin number (0–5).
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register (Table
stores interrupt requests for both vec-
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-
responding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vectored
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 2
register to determine if any interrupt requests are pending.
Table 36. Interrupt Request 2 Register (IRQ2)
BITS
FIELD
RESET
R/W
ADDR
0
R/W
0
R/W
7
6
Reserved
0
R/W
0
R/W
FC6H
5
4
3
PC3I
0
R/W
2
PC2I
0
R/W
1
PC1I
0
R/W
0
PC0I
0
R/W
Reserved—Must be 0.
PCxI—Port C Pin
x
Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin
x.
1 = An interrupt request from GPIO Port C pin
x
is awaiting service.
where
x
indicates the specific GPIO Port C pin number (0–3).
PS022815-0206
Interrupt Controller
ZILOG [ ZILOG, INC. ]
