Z8 Encore! XP® 4K Series
Product Specification
18
Table 8. Register File Address Map (Continued)
Address (Hex) Register Description
F91–FBF Reserved
Interrupt Controller
Mnemonic
Reset (Hex)
Page #
—
XX
FC0
Interrupt Request 0
IRQ0
00
00
00
00
00
00
00
00
00
XX
00
00
00
55
57
57
56
58
59
56
59
60
FC1
IRQ0 Enable High Bit
IRQ0 Enable Low Bit
Interrupt Request 1
IRQ1 Enable High Bit
IRQ1 Enable Low Bit
Interrupt Request 2
IRQ2 Enable High Bit
IRQ2 Enable Low Bit
Reserved
IRQ0ENH
IRQ0ENL
IRQ1
FC2
FC3
FC4
IRQ1ENH
IRQ1ENL
IRQ2
FC5
FC6
FC7
IRQ2ENH
IRQ2ENL
—
FC8
FC9–FCC
FCD
FCE
FCF
Interrupt Edge Select
Shared Interrupt Select
Interrupt Control
IRQES
IRQSS
IRQCTL
61
61
61
GPIO Port A
FD0
Port A Address
Port A Control
PAADDR
PACTL
PAIN
00
00
XX
00
40
42
42
42
FD1
FD2
Port A Input Data
Port A Output Data
FD3
PAOUT
GPIO Port B
FD4
Port B Address
Port B Control
PBADDR
PBCTL
PBIN
00
00
XX
00
40
42
42
42
FD5
FD6
Port B Input Data
Port B Output Data
FD7
PBOUT
GPIO Port C
FD8
Port C Address
Port C Control
PCADDR
PCCTL
PCIN
00
00
XX
00
40
42
42
42
FD9
FDA
Port C Input Data
Port C Output Data
FDB
PCOUT
GPIO Port D
FDC
Port D Address
Port D Control
Reserved
PDADDR
PDCTL
—
00
00
XX
40
42
FDD
FDE
XX=Undefined
PS022815-0206
Register Map
ZILOG [ ZILOG, INC. ]
