Z8 Encore! XP
®
4K Series
Product Specification
59
Table 42. IRQ1 Enable Low Bit Register (IRQ1ENL)
BITS
FIELD
RESET
R/W
ADDR
7
0
R/W
6
0
R/W
5
PA5ENL
0
R/W
4
PA4ENL
0
R/W
FC5H
3
PA3ENL
0
R/W
2
PA2ENL
0
R/W
1
PA1ENL
0
R/W
0
PA0ENL
0
R/W
PA7VENL PA6CENL
PA7VENL—Port A Bit[7] or LVD Interrupt Request Enable Low Bit
PA6CENL—Port A Bit[6] or Comparator Interrupt Request Enable Low Bit
PAxENL—Port A Bit[x] Interrupt Request Enable Low Bit
IRQ2 Enable High and Low Bit Registers
describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-
isters (Tables
form a priority encoded enabling for interrupts in the Interrupt
Request 2 register.
Table 43. IRQ2 Enable and Priority Encoding
IRQ2ENH[x] IRQ2ENL[x] Priority
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Description
Disabled
Low
Medium
High
where
x
indicates the register bits from 0–7.
Table 44. IRQ2 Enable High Bit Register (IRQ2ENH)
BITS
FIELD
RESET
R/W
ADDR
0
R/W
0
R/W
7
6
Reserved
0
R/W
0
R/W
FC7H
5
4
3
C3ENH
0
R/W
2
C2ENH
0
R/W
1
C1ENH
0
R/W
0
C0ENH
0
R/W
Reserved—Must be 0.
C3ENH—Port C3 Interrupt Request Enable High Bit
C2ENH—Port C2 Interrupt Request Enable High Bit
PS022815-0206
Interrupt Controller
ZILOG [ ZILOG, INC. ]
