Z8 Encore!
®
64K Series
Product Specification
22
Table 7. 64K Series Register File Address Map (Continued)
Address (Hex)
Register Description
Mnemonic
T3H
T3L
T3RH
T3RL
T3PWMH
T3PWML
T3CTL0
T3CTL1
—
U0TXD
U0RXD
U0STAT0
U0CTL0
U0CTL1
U0STAT1
U0ADDR
U0BRH
U0BRL
U1TXD
U1RXD
U1STAT0
U1CTL0
U1CTL1
U1STAT1
U1ADDR
U1BRH
U1BRL
I2CDATA
I2CSTAT
I2CCTL
I2CBRH
I2CBRL
I2CDST
I2CDIAG
—
Reset (Hex)
00
01
FF
FF
00
00
00
00
XX
XX
XX
0000011Xb
00
00
00
00
FF
FF
XX
XX
0000011Xb
00
00
00
00
FF
FF
00
80
00
FF
FF
C0
00
XX
Page #
Timer 3 (unavailable in the 44-pin packages)
F18
Timer 3 High Byte
F19
Timer 3 Low Byte
F1A
Timer 3 Reload High Byte
F1B
Timer 3 Reload Low Byte
F1C
Timer 3 PWM High Byte
F1D
Timer 3 PWM Low Byte
F1E
Timer 3 Control 0
F1F
Timer 3 Control 1
20-3F
Reserved
UART 0
F40
F41
F42
F43
F44
F45
F46
F47
UART 1
F48
F49
F4A
F4B
F4C
F4D
F4E
F4F
I
2
C
F50
F51
F52
F53
F54
F55
F56
F57-F5F
XX=Undefined
UART0 Transmit Data
UART0 Receive Data
UART0 Status 0
UART0 Control 0
UART0 Control 1
UART0 Status 1
UART0 Address Compare Register
UART0 Baud Rate High Byte
UART0 Baud Rate Low Byte
UART1 Transmit Data
UART1 Receive Data
UART1 Status 0
UART1 Control 0
UART1 Control 1
UART1 Status 1
UART1 Address Compare Register
UART1 Baud Rate High Byte
UART1 Baud Rate Low Byte
I
2
C Data
I
2
C Status
I
2
C Control
I
2
C Baud Rate High Byte
I
2
C Baud Rate Low Byte
I
2
C Diagnostic State
I
2
C Diagnostic Control
Reserved
PS019915-1005
Register File Address Map
ZILOG [ ZILOG, INC. ]
