Z8 Encore!
®
64K Series
Product Specification
23
Table 7. 64K Series Register File Address Map (Continued)
Address (Hex)
Register Description
Mnemonic
SPIDATA
SPICTL
SPISTAT
SPIMODE
SPIDST
—
SPIBRH
SPIBRL
—
ADCCTL
—
ADCD_H
ADCD_L
—
DMA0CTL
DMA0IO
DMA0H
DMA0START
DMA0END
DMA1CTL
DMA1IO
DMA1H
DMA1START
DMA1END
Reset (Hex)
XX
00
01
00
00
XX
FF
FF
XX
20
XX
XX
XX
XX
00
XX
XX
XX
XX
00
XX
XX
XX
XX
Page #
Serial Peripheral Interface (SPI)
F60
SPI Data
F61
SPI Control
F62
SPI Status
F63
SPI Mode
F64
SPI Diagnostic State
F65
Reserved
F66
SPI Baud Rate High Byte
F67
SPI Baud Rate Low Byte
F68-F6F
Reserved
Analog-to-Digital Converter (ADC)
F70
ADC Control
F71
Reserved
F72
ADC Data High Byte
F73
ADC Data Low Bits
F74-FAF
Reserved
DMA 0
FB0
FB1
FB2
FB3
FB4
DMA 1
FB8
FB9
FBA
FBB
FBC
DMA ADC
FBD
FBE
FBF
DMA0 Control
DMA0 I/O Address
DMA0 End/Start Address High Nibble
DMA0 Start Address Low Byte
DMA0 End Address Low Byte
DMA1 Control
DMA1 I/O Address
DMA1 End/Start Address High Nibble
DMA1 Start Address Low Byte
DMA1 End Address Low Byte
DMA_ADC Address
DMA_ADC Control
DMA_ADC Status
DMAA_ADDR XX
DMAACTL
00
DMAASTAT 00
IRQ0
IRQ0ENH
IRQ0ENL
IRQ1
IRQ1ENH
IRQ1ENL
IRQ2
00
00
00
00
00
00
00
Interrupt Controller
FC0
Interrupt Request 0
FC1
IRQ0 Enable High Bit
FC2
IRQ0 Enable Low Bit
FC3
Interrupt Request 1
FC4
IRQ1 Enable High Bit
FC5
IRQ1 Enable Low Bit
FC6
Interrupt Request 2
XX=Undefined
PS019915-1005
Register File Address Map
ZILOG [ ZILOG, INC. ]
