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Z8F2421VN020EC 参数 Datasheet PDF下载

Z8F2421VN020EC图片预览
型号: Z8F2421VN020EC
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能8位微控制器Z8喝采! -R 64K系列 [High Performance 8-Bit Microcontrollers Z8 Encore!-R 64K Series]
分类和应用: 微控制器
文件页数/大小: 299 页 / 1995 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore!® 64K Series  
Product Specification  
145  
Write Transaction with a 7-Bit Address  
Figure 29 illustrates the data transfer format for a 7-bit addressed slave. Shaded regions  
indicate data transferred from the I2C Controller to slaves and unshaded regions indicate  
data transferred from the slaves to the I2C Controller.  
S
Slave Address W = 0  
A
Data  
A
Data  
A
Data  
A/A P/S  
Figure 29. 7-Bit Addressed Slave Data Transfer Format  
The procedure for a transmit operation to a 7-bit addressed slave is as follows:  
1. Software asserts the IENbit in the I2C Control register.  
2. Software asserts the TXIbit of the I2C Control register to enable Transmit interrupts.  
3. The I2C interrupt asserts, because the I2C Data register is empty  
4. Software responds to the TDREbit by writing a 7-bit slave address plus write bit (=0)  
to the I2C Data register.  
5. Software asserts the START bit of the I2C Control register.  
6. The I2C Controller sends the START condition to the I2C slave.  
7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data  
register.  
8. After one bit of address has been shifted out by the SDA signal, the Transmit interrupt  
is asserted (TDRE = 1).  
9. Software responds by writing the transmit data into the I2C Data register.  
10. The I2C Controller shifts the rest of the address and write bit out by the SDA signal.  
11. If the I2C slave sends an acknowledge (by pulling the SDA signal low) during the next  
high period of SCL the I2C Controller sets the ACKbit in the I2C Status register.  
Continue with step 12.  
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is  
set in the Status register, ACK bit is cleared). Software responds to the Not  
Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit.  
The I2C Controller sends the STOP condition on the bus and clears the STOP and  
NCKI bits. The transaction is complete (ignore following steps).  
12. The I2C Controller loads the contents of the I2C Shift register with the contents of the  
I2C Data register.  
PS019915-1005  
I2C Controller