欢迎访问ic37.com |
会员登录 免费注册
发布采购

Z8F2421VN020EC 参数 Datasheet PDF下载

Z8F2421VN020EC图片预览
型号: Z8F2421VN020EC
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能8位微控制器Z8喝采! -R 64K系列 [High Performance 8-Bit Microcontrollers Z8 Encore!-R 64K Series]
分类和应用: 微控制器
文件页数/大小: 299 页 / 1995 K
品牌: ZILOG [ ZILOG, INC. ]
 浏览型号Z8F2421VN020EC的Datasheet PDF文件第162页浏览型号Z8F2421VN020EC的Datasheet PDF文件第163页浏览型号Z8F2421VN020EC的Datasheet PDF文件第164页浏览型号Z8F2421VN020EC的Datasheet PDF文件第165页浏览型号Z8F2421VN020EC的Datasheet PDF文件第167页浏览型号Z8F2421VN020EC的Datasheet PDF文件第168页浏览型号Z8F2421VN020EC的Datasheet PDF文件第169页浏览型号Z8F2421VN020EC的Datasheet PDF文件第170页  
Z8 Encore!® 64K Series  
Product Specification  
146  
13. The I2C Controller shifts the data out of using the SDA signal. After the first bit is  
sent, the Transmit interrupt is asserted.  
14. If more bytes remain to be sent, return to step 9.  
15. Software responds by setting the STOPbit of the I2C Control register (or START bit  
to initiate a new transaction). In the STOP case, software clears the TXIbit of the I2C  
Control register at the same time.  
16. The I2C Controller completes transmission of the data on the SDA signal.  
17. The slave may either Acknowledge or Not Acknowledge the last byte. Because either  
the STOP or START bit is already set, the NCKI interrupt does not occur.  
18. The I2C Controller sends the STOP (or RESTART) condition to the I2C bus. The  
STOP or START bit is cleared.  
Address Only Transaction with a 10-bit Address  
In the situation where software wants to determine if a slave with a 10-bit address is  
responding without sending or receiving data, a transaction can be done which only con-  
sists of an address phase. Figure 30 illustrates this “address only” transaction to determine  
if a slave with 10-bit address will acknowledge. As an example, this transaction can be  
used after a “write” has been done to a EEPROM to determine when the EEPROM com-  
pletes its internal write operation and is once again responding to I2C transactions. If the  
slave does not Acknowledge the transaction can be repeated until the slave is able to  
Acknowledge.  
Slave Address  
1st 7 bits  
Slave Address  
2nd Byte  
S
W = 0 A/A  
A/A P  
Figure 30. 10-Bit Address Only Transaction Format  
The procedure for an address only transaction to a 10-bit addressed slave is as follows:  
1. Software asserts the IENbit in the I2C Control register.  
2. Software asserts the TXIbit of the I2C Control register to enable Transmit interrupts.  
3. The I2C interrupt asserts, because the I2C Data register is empty (TDRE = 1)  
4. Software responds to the TDREinterrupt by writing the first slave address byte. The  
least-significant bit must be 0 for the write operation.  
5. Software asserts the START bit of the I2C Control register.  
6. The I2C Controller sends the START condition to the I2C slave.  
PS019915-1005  
I2C Controller