Z8 Encore!
®
64K Series
Product Specification
56
PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control reg-
ister.
PADDR[7:0]
00H
01H
02H
03H
04H
05H
06H-FFH
Port Control sub-register accessible using the Port A-H Control Registers
No function. Provides some protection against accidental Port reconfiguration.
Data Direction
Alternate Function
Output Control (Open-Drain)
High Drive Enable
STOP Mode Recovery Source Enable.
No function.
Port A-H Control Registers
The Port A–H Control registers set the GPIO port operation. The value in the correspond-
ing Port A–H Address register determines the control sub-registers accessible using the
Port A–H Control register (Table 15).
Table 15. Port A
–
H Control Registers (PxCTL)
BITS
FIELD
RESET
R/W
ADDR
7
6
5
4
PCTL
00H
R/W
3
2
1
0
FD1H, FD5H, FD9H, FDDH, FE1H, FE5H, FE9H, FEDH
PCTL[7:0]—Port Control
The Port Control register provides access to all sub-registers that configure the GPIO Port
operation.
PS019915-1005
General-Purpose I/O
ZILOG [ ZILOG, INC. ]
