Z8 Encore!
®
64K Series
Product Specification
21
Register File Address Map
devices and package styles in the 64K Series support Timer 3 and all of the GPIO Ports.
Consider registers for unimplemented peripherals as Reserved.
Table 7. 64K Series Register File Address Map
Address (Hex)
Register Description
Mnemonic
—
T0H
T0L
T0RH
T0RL
T0PWMH
T0PWML
T0CTL0
T0CTL1
T1H
T1L
T1RH
T1RL
T1PWMH
T1PWML
T1CTL0
T1CTL1
T2H
T2L
T2RH
T2RL
T2PWMH
T2PWML
T2CTL0
T2CTL1
Reset (Hex)
XX
00
01
FF
FF
00
00
00
00
00
01
FF
FF
00
00
00
00
00
01
FF
FF
00
00
00
00
Page #
General Purpose RAM
000-EFF
General-Purpose Register File RAM
Timer 0
F00
F01
F02
F03
F04
F05
F06
F07
Timer 1
F08
F09
F0A
F0B
F0C
F0D
F0E
F0F
Timer 2
F10
F11
F12
F13
F14
F15
F16
F17
XX=Undefined
Timer 0 High Byte
Timer 0 Low Byte
Timer 0 Reload High Byte
Timer 0 Reload Low Byte
Timer 0 PWM High Byte
Timer 0 PWM Low Byte
Timer 0 Control 0
Timer 0 Control 1
Timer 1 High Byte
Timer 1 Low Byte
Timer 1 Reload High Byte
Timer 1 Reload Low Byte
Timer 1 PWM High Byte
Timer 1 PWM Low Byte
Timer 1 Control 0
Timer 1 Control 1
Timer 2 High Byte
Timer 2 Low Byte
Timer 2 Reload High Byte
Timer 2 Reload Low Byte
Timer 2 PWM High Byte
Timer 2 PWM Low Byte
Timer 2 Control 0
Timer 2 Control 1
PS019915-1005
Register File Address Map
ZILOG [ ZILOG, INC. ]
