Z8 Encore!
®
64K Series
Product Specification
64
Architecture
Port Interrupts
Interrupt Request Latches and Control
High
Priority
Vector
Priority
Mux
IRQ Request
Medium
Priority
Internal Interrupts
Low
Priority
Figure 11. Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
•
•
•
•
•
•
•
Executing an EI (Enable Interrupt) instruction
Executing an IRET (Return from Interrupt) instruction
Writing a 1 to the
IRQE
bit in the Interrupt Control register
Execution of a DI (Disable Interrupt) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt
controller
Writing a 0 to the
IRQE
bit in the Interrupt Control register
Reset
Interrupts are globally disabled by any of the following actions:
PS019915-1005
Interrupt Controller
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