U6264B
Switching Characteristics
Alt.
Time to Output in Low-Z
Cycle Time
Write Cycle Time
Read Cycle Time
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
Data Hold Time
Address Hold from End of Write
Output Hold Time from Address Change
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
t
LZ
t
WC
t
RC
t
ACE
t
OE
t
AA
t
WP
t
CW
t
AS
t
CW
t
WP
t
DS
t
DH
t
AH
t
OH
t
HZCE
t
HZWE
t
HZOE
Symbol
IEC
t
t(QX)
t
cW
t
cR
t
a(E)
t
a(G)
t
a(A)
t
w(W)
t
w(E)
t
su(A)
t
su(E)
t
su(W)
t
su(D)
t
h(D)
t
h(A)
t
v(A)
t
dis(E)
t
dis(W)
t
dis(G)
Min.
5
70
70
-
-
-
50
65
0
65
50
35
0
0
5
0
0
0
25
30
25
70
40
70
Max.
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Mode E1-Controlled
4.5 V
V
CC(DR)
≥
2 V
2.2 V
t
DR
0V
Data Retention
t
rec
2.2 V
E1
0V
V
CC
Data Retention Mode E2-Controlled
V
CC
V
CC(DR)
≥
2 V
t
DR
0.8 V
Data Retention
V
E2(DR)
≤
0.2 V
t
rec
0.8 V
E2
4.5 V
V
E2(DR)
≥
V
CC(DR)
- 0.2 V or V
E2(DR)
≤
0.2 V
V
CC(DR)
- 0.2 V
≤
V
E1(DR)
≤
V
CC(DR)
+ 0.3 V
Chip Deselect to Data Retention Time
Operating Recovery Time
t
DR
:
t
rec
:
min 0 ns
min t
cR
April 20, 2004
5
ZMD [ Zentrum Mikroelektronik Dresden AG ]
