U62H64
Read Cycle 1 (during Read cycle: E1 = G = V
IL
, E2 = W = V
IH
, A
i
-controlled)
t
cR
A
i
DQ
i
Output
Previous Data Valid
t
v(A)
Addresses Valid
t
a(A)
Output Data Valid
Read Cycle 2 (during Read cycle: W = V
IH
, G-, E1- or E2-controlled)
t
cR
A
i
E1
t
su(A)
Addresses Valid
t
a(E)
t
en(E)
t
su(A)
t
a(E)
t
en(E)
t
a(G)
t
dis(G)
High-Z
t
PU
50 %
*
t
dis(E)
t
dis(E)
E2
G
DQ
i
Output
t
en(G)
Output Data Valid
t
PD*
50 %
I
CC(OP)
I
CC(SB)
* The same applies to E1
Write Cycle 1 (W-controlled)
t
cW
A
i
E1
E2
W
DQ
i
Input
t
dis(W)
t
su(A)
Addresses Valid
t
su(E)
t
h(A)
t
su(E)
t
w(W)
t
su(D)
t
h(D)
t
en(W)
Input Data Valid
High-Z
DQ
i
Output
G
April 20, 2004
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