U62H64
Write Cycle 2 (E1-controlled)
tcW
Ai
Addresses Valid
tw(E)
tsu(A)
th(A)
E1
E2
E2
W
tsu(E)
tsu(W)
tsu(D)
th(D)
DQi
Input Data Valid
Input
tdis(W)
ten(E)
DQi
High-Z
Output
G
Write Cycle 3 (E2-controlled)
tcW
Addresses Valid
tsu(E)
Ai
th(A)
E1
tsu(A)
tw(E)
E2
W
tsu(W)
tsu(D)
th(D)
DQi
Input Data Valid
Input
tdis(W)
ten(E)
High-Z
DQi
Output
G
L- or H-level
undefined
The information describes the type of component and shall not be considered as assured characteristic. Terms of
delivery and rights to change design reserved.
8
April 20, 2004