U634H256
PowerStore
and Automatic Power Up RECALL
V
CAP
V
SWITCH
5.0 V
t
PowerStore
Power Up
RECALL
W
DQi
POWER UP BROWN OUT
NO STORE
RECALL
(NO SRAM WRITES)
Hardware Controlled STORE
t
w(H)Sq
(28)
t
en(H)S
(27)
t
dis(H)S
(26)
Previous Data Valid
t
d(H)S
(25)
High Impedance
Data Valid
t
PDSTOREp
(24)
(24)
t
RESTOR
E
t
RESTORE
t
DELAYp
BROWN OUT
PowerStore
HSB
DQi
Output
Software Controlled STORE/RECALL
No.
Cycle
29 STORE/RECALL Initiation Time
30 Chip Enable to Output Inactive
s
31 STORE Cycle Time
32 RECALL Cycle Time
r
33 Address Setup to Chip Enable
t
34 Chip Enable Pulse Width
s, t
35 Chip Disable to Address Change
t
Symbol
Alt.
t
AVAV
t
ELQZ
t
ELQXS
t
ELQXR
t
AVELN
t
ELEHN
t
EHAXN
IEC
t
cR
t
dis(E)SR
t
d(E)S
t
d(E)R
t
su(A)SR
t
w(E)SR
t
h(A)SR
0
20
0
25
35
45
Unit
Min. Max. Min. Max. Min. Max.
25
600
10
20
0
25
0
35
600
10
20
0
30
0
45
600
10
20
ns
ns
ms
µs
ns
ns
ns
p: t
PDSTORE
approximate t
d(E)S
or t
d(H)S
; t
DELAY
approximate t
dis(H)S
.
q: After t
w(H)S
HSB is hold down internal by STORE operation.
r: An automatic RECALL also takes place at power up, starting when V
CC
exceeds V
SWITCH
and takes t
RESTORE
. V
CC
must not drop below
V
SWITCH
once it has been exceeded for the RECALL to function properly.
s: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
t: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
8
April 21, 2004
ZMD [ Zentrum Mikroelektronik Dresden AG ]
