Datasheet
ZADCS146 / ZADCS147
Figure 4: Block diagram of input multiplexer
Shown configuration
A2 … A0 = 0x000
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Figure 5: Input voltage range in unipolar mode
V
IN+
1.5*V
REF
0xFFF
V
REF
Code Range
IN+
Converter
IN-
0.5*V
REF
0x000
0V
V
DD
-V
REF
V
IN-
Figure 6: Input voltage range for fully differen-
tial signals in bipolar mode
V
CM
V
REF
¾ V
REF
V
CM
COM
See Table 3 & Table 4
for Coding Schemes
SGL/DIF = HIGH
0V
-V
REF
/2
0V
+V
REF
/2
V
DIFF
¼ V
REF
Range
voltage at IN
–
to obtain codes unequal to 0x000. The
entire 12 bit transfer characteristic is then covered by IN
+
if IN
+
ranges from IN
–
to (IN
–
+Vref). Any voltage on
IN
+
> (IN
–
+ Vref) results in code 0xFFF. Code 0xFFF is
not reached, if (IN
–
+Vref) > VDD + 0.2V because the
input voltage is clamped at VDD + 0.2V by ESD protec-
tion devices.
The voltage at IN
–
can range from -0.2V … �½ V
REF
with-
out limiting the Code Range, assuming the fore men-
tioned VDD condition is true. See also Figure 5 for input
voltage ranges in unipolar conversion mode.
In bipolar mode, IN
+
can range from (IN
–
- Vref/2) to (IN
–
+ Vref/2) keeping the converter out of code saturation.
For instance, if IN
–
is set to a constant DC voltage of
Vref/2, then IN
+
can vary from 0V to Vref to cover the
entire code range. Lower or higher voltages of IN
+
keep
the output code at the minimum or maximum code value.
Figure 6 shows the input voltage ranges in bipolar mode
when IN
–
is set to a constant DC voltage.
As explained before, ZADCS146 / ZADCS147 can also
be used to convert fully differential input signals that
change around a common mode input voltage.
The bipolar mode is best used for such purposes since it
allows the input signals to be positive or negative in rela-
tion to each other.
The common mode level of a differential input signal is
calculated V
CM
= (V(IN
+
)+ V(IN
–
)) / 2. To avoid code clip-
ping or over steering of the converter, the common mode
level can change from ¼ Vref … ¾ Vref. Within this range
the peak to peak amplitude of the differential input signal
can be ± Vref/2.
The average input current on the analog inputs depends
on the conversion rate. The signal source must be capa-
ble of charging the internal sampling capacitors (typically
16pF on each input of the converter: IN
+
and IN
–
) within
the acquisition time t
ACQ
to the required accuracy. The
equivalent input circuit in sampling mode is shown in
Figure 7.
The following equation provides a rough hand calculation
for a source impedance R
S
that is required to settle out a
DC input signal referenced to AGND with 12 bit accuracy
in a given acquisition time
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
Channel
Multiplexer
C
HOLD+
IN
+
C
IN
4pF 16pF
AGND
R
SW
3kΩ
C
HOLD-
IN
-
C
IN
4pF 16pF
AGND
R
SW
3kΩ
V
DC
Figure 7: Equivalent input circuit during sampling
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
11/19
ZMD [ Zentrum Mikroelektronik Dresden AG ]
