Datasheet
ZADCS146 / ZADCS147
1.3.3 ZADCS147 Specific Parameters
(VDD = +2.7V to + 5.25V; f
SCLK
= 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps);
q
OP
=
q
OPmin
…
q
OPmax
)
Parameter
External Reference at VREF
VREF Input Voltage Range
VREF Input Current
VREF Input Resistance
Shutdown VREF Input Current
Capacitive Bypass at VREF
Symbol Conditions
Min
Typ
Max
Unit
1.0
VREF = 2.5V
11.5
180
14
VDD +
V
50mV
215
µA
kW
0.1
µA
µF
4.7
Power Requirements
Positive Supply Voltage
Positive Supply Current
VDD
IDD
VDD = 3.6V
VDD
5.25V
Operating Mode
Full Power-Down
2.7
0.85
0.5
1.00
0.5
5.25
1.0
4.0
1.3
4.0
V
µA
Positive Supply Current
IDD
= Operating Mode
Full Power-Down
µA
1.3.4 ZADCS146 / ZADCS147 Digital Pin Parameters
(VDD = +2.7V to + 5.25V; f
SCLK
= 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps);
q
OP
=
q
OPmin
…
q
OPmax
)
Parameter
Symbol Conditions
Min
Typ
Max
Unit
Digital Inputs (DIN, SCLK, CS, nSHDN)
Logic High Level
V
IH
V
IL
V
Hyst
I
IN
I
IN_nSHDN
C
IN
VIN = 0V or VDD
VIN = 0V
5
VDD = 2.7V
VDD = 5.25V
VDD = 2.7V
VDD = 5.25V
0.7
± 0.1
± 1.0
- 5.0
1.9
3.3
0.7
1.4
V
V
V
V
V
µA
µA
pF
Logic Low Level
Hysteresis
Input Leakage
Input Low Leakage @ nSHDN
Input Capacitance
Digital Outptus (DOUT, SSTRB)
Output High Current
I
OH
I
OL
I
Leak
C
OUT
V
OH
= VDD – 0.5V
V
OL
= 0.4V
nCS = VDD
nCS = VDD
VDD = 2.7V
VDD = 5.25V
VDD = 2.7V
VDD = 5.25V
3.5
5.5
4
6.4
± 0.1
5
8.5
10.8
11.5
15.3
± 1.0
mA
mA
mA
mA
µA
pF
Output Low Current
Three-State Leakage Current
Three-State Output Capacitance
Copyright © 2008, ZMD AG, Rev. 1.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
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ZMD [ Zentrum Mikroelektronik Dresden AG ]
