UCC15701/2
UCC25701/2
UCC35701/2
DETAILED BLOCK DIAGRAM
2*I
RT
S
VFF
6
Q
RT
CT
7
I
RT
10
PWM
0.2V
VALLEY
S
R
D
5
VSCLAMP
9
4V
V
REF
I
SS
14
0.6V
ILIM
2
0.2V
D
PWM
SSDONE
COUNT
1
R
4V
13 GND
SHUTDOWN
LATCH
Q
CURRENT FAULT
25*I
R
S
D
I
R
S
D
Q
FAULT
LATCH
5.0V
REF
Q
0.6V
SSDONE
HIGH LINE
RUN
LOW LINE
13/9V (35701)
9.6/8.8V (35702)
4.5V
PGND
Q
4
OUT
PEAK
3
VDD
R
D
3µA
11
SYNC
0.7V
+
FB
8
1.5R
R
CURRENT LIMIT
V
REF
0.2V
VDD
12 VREF
UDG-98004
PIN DESCRIPTIONS
VDD:
Power supply pin. A shunt regulator limits supply
voltage to 14V typical at 10mA shunt current.
PGND:
Power Ground. Ground return for output driver
and currents.
GND:
Analog Ground. Ground return for all other circuits.
This pin must be connected directly to PGND on the
board.
OUT:
Gate drive output. Output resistance is 10Ω maxi-
mum.
VFF:
Voltage feedforward pin. This pin connects to the
power supply input voltage through a resistive divider and
provides feedforward compensation over a 0.8V to 3.2V
range. A voltage greater than 4.0V or less than 0.6V on
this pin initiates a soft stop cycle.
4
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RT:
The voltage on this pin mirrors VFF over a 0.8V to
3.2V range. A resistor to ground sets the ramp capacitor
charge current. The resistor value should be between
20k and 200k.
CT:
A capacitor to ground provides the oscillator/
feedforward sawtooth waveform. Charge current is 2
•
I
RT
, resulting in a CT slope proportional to the input volt-
age. The ramp voltage range is GND to V
RT
.
Period and oscillator frequency is given by:
T
=
F
≈
V
RT
•
C
T
+
t
DISCH
≈
0 .5
•
R
T
•
C
T
2
•
I
RT
2
RT
•
CT
ETC [ ETC ]
