93LC46A/B
2.0
2.1
PIN DESCRIPTION
Chip Select (CS)
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a START condition the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (Table 2-1
and Table 2-2). CLK and DI then become don't care
inputs waiting for a new START condition to be
detected.
A high level selects the device; a low level deselects the
device and forces it into standby mode. However, a pro-
gramming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (T
CSL
) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.3
Data In (DI)
Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.2
Serial Clock (CLK)
2.4
Data Out (DO)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93LC46AX/
BX. Opcodes, address, and data bits are clocked in on
the positive edge of CLK. Data bits are also clocked out
on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
CKH
) and
clock low time (T
CKL
). This gives the controlling master
freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
Data Out (DO) is used in the READ mode to output
data synchronously with the CLK input (T
PD
after the
positive edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (T
CSL
) and an ERASE or WRITE operation
has been initiated.
The status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
TABLE 2-1
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
INSTRUCTION SET FOR 93LC46A
SB
1
1
1
1
1
1
1
Opcode
11
00
00
00
10
01
00
A6
1
0
1
A6
A6
0
A5
0
0
1
A5
A5
1
Address
A4
X
X
X
A4
A4
X
A3
X
X
X
A3
A3
X
A2
X
X
X
A2
A2
X
A1
X
X
X
A1
A1
X
A0
X
X
X
A0
A0
X
Data In
—
—
—
—
—
D7 - D0
D7 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D7 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
10
10
10
10
18
18
18
TABLE 2-2
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
INSTRUCTION SET FOR 93LC46B
SB
1
1
1
1
1
1
1
Opcode
11
00
00
00
10
01
00
A5
1
0
1
A5
A5
0
A4
0
0
1
A4
A4
1
Address
A3
X
X
X
A3
A3
X
A2
X
X
X
A2
A2
X
A1
X
X
X
A1
A1
X
A0
X
X
X
A0
A0
X
Data In
—
—
—
—
—
D15 - D0
D15 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D15 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
9
9
9
9
25
25
25
©
1998 Microchip Technology Inc.
DS21173E-page 3
ETC [ ETC ]
